Bit Vector Scanning for Packet Processor Feature Flags

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Solution Overview

Problem

Conventional multi-threaded packet processors experience high processing latency due to the overhead of testing feature flags, especially when only a few features are enabled, as they need to evaluate all disabled flags, requiring multiple instructions.

Innovation Solution

Implementing a method that uses bit vector scanning to detect and execute enabled feature flags with a single instruction, where each bit in the bit vector represents a feature or conditional status, allowing for zero-overhead processing by scanning, setting, and looking up instruction addresses until all bits are cleared.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multi-threaded packet processors test feature flags one by one to determine enabled features, then all feature flags can be evaluated, but processing latency increases significantly when only a few features are enabled

Engineering Contradiction:

Improvefeature flag evaluation completenessVSAvoidprocessing latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the conventional sequential mechanical testing of feature flags with a bit vector scanning mechanism that uses parallel bit manipulation instructions. This substitution allows the processor to efficiently identify enabled features without evaluating all flags sequentially, thereby reducing processing latency while maintaining complete feature evaluation capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the representation of feature flags from sequential boolean tests to a compact bit vector format where each bit corresponds to a feature flag. This parameter change enables parallel processing of feature evaluation through bit scanning operations, transforming the time complexity from O(n) sequential checks to O(log n) parallel operations.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If multiple instructions are used to test each feature flag, then accurate feature detection is achieved, but instruction overhead increases

Engineering Contradiction:

Improvefeature detection accuracyVSAvoidinstruction overhead

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple feature flag testing instructions into a single bit vector scanning operation. By combining the detection of multiple features into one parallel operation, the system achieves accurate feature detection without the accumulated overhead of multiple sequential instructions, thereby reducing device complexity while maintaining measurement precision.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bit vector scanning mechanism serves as a universal approach that can detect any enabled feature flag within the vector simultaneously. This multi-functional instruction replaces multiple specialized testing instructions, achieving feature detection accuracy while minimizing instruction overhead through a single versatile operation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If all disabled feature flags are evaluated to find enabled ones, then complete feature status is determined, but processing efficiency decreases

Engineering Contradiction:

Improvefeature status determinationVSAvoidpacket processing throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements a bit scanning algorithm that skips over disabled feature flags (bits set to zero) and directly identifies enabled features (bits set to one). This skipping mechanism allows the processor to determine complete feature status without evaluating every disabled flag sequentially, thereby maintaining reliability while significantly improving packet processing throughput.

Inventive Principle:

Principle #21Skipping (Rushing through)

Solution Approach 2:

The bit vector is pre-configured with feature flag statuses during system initialization, allowing the scanning mechanism to immediately identify enabled features without performing exhaustive evaluation during packet processing. This preliminary action ensures complete feature status determination is available in advance, improving productivity during actual packet processing operations.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9152423B2Method and apparatus for efficient loop instruction execution using bit vector scanning

Publication Date: 2015.10.06 EXTREME NETWORKS INC

AI summary

A method, apparatus and computer program product for performing efficient loop instruction execution using bit vector scanning is presented. A bit vector is scanned, each bit in the bit vector representing at least one of a feature and a conditional status. The presence of a bit of said bit vector set to a first state is detected. The bit is set to a second state. An instruction address for a routine corresponding to said bit set to a first state is looked up using a bit position of said bit that was set to a first state. The routine is executed. The scanning, said detecting, said setting and said using are repeated until there are no remaining bits of said bit vector set to said first state.