Register Arrangements TRIZ Cases
- Processor Execution Unit Segmentation for Wiring Space Reduction
Segmenting execution units to handle immediate values reduces register file read paths, cutting wiring space and propagation delays.
- Partitioned Register File With Dual Memory Structures
Segmenting the register file into low-energy latches and high-capacity SRAM reduces access energy by one-third while maintaining storage capacity.
- Microcomputer Data Transfer Apparatus Register File Check
A data transfer apparatus checks a status register to select pre-loaded transfer information from internal register files.
- Programmable Filter Processor Pipeline Parallelism
Pipelined logic stages process signal data in parallel, resolving the contradiction between real-time processing speed and device complexity.
- Register Renaming via Dual-Channel Segmentation
Segmenting register renaming into parallel and sequential phases reduces gate count and power consumption while maintaining pipeline throughput.
- Shaped Register File Reads via Crossbar Switching
A register file uses a crossbar switch to enable shaped access of variable-sized data operands from multiple 32-bit slots.
- Transactional Memory Register Checkpointing via Rename Logic
Rename logic maps architectural registers to physical storage, reducing checkpointing latency and resource overhead in transactional memory systems.
- Vector Packed Multiplication for Dual Signed Unsigned Data
A processor executes concurrent dual signed and unsigned multiplication of packed byte elements using unified vector instructions.
- Vector Register Access Circuitry for Parallel Data Processing
Column-based register organization with dedicated access blocks resolves instruction execution bottlenecks by enabling parallel component retrieval.
- Centralized Access Control Circuit for SoC Peripheral Security
Consolidating distributed security units into a single circuit reduces area and latency while enabling dynamic, scalable protection for multiple peripherals.