Partitioned Register File With Dual Memory Structures
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Solution Overview
Problem
Register file access energy consumption is a significant fraction of system energy usage due to the capacity constraints of existing memory technologies, necessitating a solution to reduce overall energy usage while maintaining or improving storage capacity.
Innovation Solution
Implementing a register file with a dual memory structure, comprising a low-energy array of latches and a high-capacity SRAM, and using a single logical namespace for both, where frequently accessed values are allocated to the low-energy structure and less frequently accessed values to the high-capacity SRAM, based on compiler-projected access frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single memory structure is used for the register file, then the device complexity is reduced, but the access energy consumption increases due to capacity constraints
Solution Approach 1:
The register file is segmented into two distinct memory structures: a first memory structure with lower access energy and a second memory structure with higher storage capacity. This segmentation allows the system to optimize between energy consumption and storage capacity by dividing the register file functionality across two specialized structures rather than using a single compromise structure.
Solution Approach 2:
Different regions of the register file are assigned different memory structures based on their access patterns. Frequently accessed registers are mapped to the low-energy first memory structure, while less frequently accessed registers are mapped to the high-capacity second memory structure. This local quality differentiation optimizes energy consumption for hot data while maintaining capacity for cold data.
2Ease of operation
If a single logical namespace is used for both memory structures, then the ease of operation is improved, but the device complexity increases due to mapping requirements
Solution Approach 1:
The patent merges the namespace of both memory structures into a single logical namespace. This allows the compiler to allocate registers to a unified address space without needing to manage separate namespaces for different memory structures. The mapping between the single logical namespace and the two physical memory structures is handled by the processing unit, simplifying compiler allocation while maintaining operational ease.
3Use of energy by moving object
If frequently accessed values are allocated to the low-energy structure, then the access energy is reduced, but the storage capacity for less frequently accessed values is limited
Solution Approach 1:
The system dynamically determines the number of register addresses per thread to map to each memory structure at runtime. This dynamic allocation allows the system to adapt to varying workloads and optimize the split between low-energy and high-capacity structures based on actual access patterns, rather than using a fixed static allocation.
Solution Approach 2:
The patent changes the allocation parameter from uniform distribution to frequency-based distribution. By using compiler-projected frequency of access as the allocation criterion, the system assigns more register addresses to the low-energy first memory structure for frequently accessed values, and fewer addresses to the second memory structure for less frequently accessed values, optimizing the energy-capacity tradeoff.
Data Source
AI summary
A system includes a processing unit and a register file. The register file includes at least a first memory structure and a second memory structure. The first memory structure has a lower access energy than the second memory structure. The processing unit is configured to address the register file using a single logical namespace for both the first memory structure and the second memory structure.