Microcomputer Data Transfer Apparatus Register File Check

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Solution Overview

Problem

Existing data transfer apparatuses in microcomputers, while efficient, face limitations in handling multiple interrupts and events due to stored data transfer information in RAM, leading to inefficiencies in CPU load and data transfer acceleration, especially when transfer factors remain constant, and have limitations in bit manipulation procedures.

Innovation Solution

A data transfer apparatus that checks a status register to determine whether to use pre-set transfer information in register files or read from storage, allowing for flexible and accelerated data transfer by omitting unnecessary read/write operations and enabling bit manipulation through specified operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data transfer information is stored in RAM and read upon interrupt occurrence, then the data transfer apparatus can handle various purposes with flexibility, but the read operation consumes time and reduces data transfer acceleration

Engineering Contradiction:

Improveflexibility in handling various purposesVSAvoidtime for read operation

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The data transfer information is pre-loaded into the data transfer apparatus before interrupt occurrence. When an interrupt occurs, the apparatus already has the necessary transfer source address, transfer destination address, and transfer number ready, eliminating the need for time-consuming read operations during the interrupt handling process.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If the CPU performs interrupt handling and data transfer processing, then any processing can be realized through instructions, but the CPU load increases and processing speed decreases

Engineering Contradiction:

Improveprocessing capability through instructionsVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The data transfer function is extracted from the CPU and implemented as a dedicated data transfer apparatus. This separates the data transfer processing from the CPU, allowing the CPU to focus on control processing while the dedicated apparatus handles data transfer, thereby reducing CPU load and improving overall processing speed.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The data transfer apparatus autonomously performs data transfer operations based on pre-loaded transfer information without requiring CPU intervention during the actual transfer process. The apparatus self-manages the transfer execution, further reducing CPU load and improving productivity.

Inventive Principle:

Principle #25Self-service

3Productivity

If a dedicated data transfer apparatus is used instead of CPU for data transfer, then data transfer speed increases and CPU load decreases, but the apparatus requires more hardware elements

Engineering Contradiction:

Improvedata transfer speedVSAvoidnumber of hardware elements

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The data transfer apparatus is designed with multi-functionality to handle various data transfer purposes using a unified structure. By implementing universal transfer information storage and processing capabilities, the apparatus can serve multiple functions without requiring separate hardware for each purpose, thereby limiting the increase in hardware elements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If data transfer information is read from storage apparatus upon interrupt, then the system can handle multiple interrupts and events, but the CPU load increases due to frequent read operations

Engineering Contradiction:

Improvecapability to handle multiple interruptsVSAvoidCPU load

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

Transfer information is pre-loaded into the data transfer apparatus before interrupts occur. This preliminary action eliminates the need for repeated read operations from storage apparatus during interrupt handling, significantly reducing CPU load and energy consumption while maintaining the capability to handle multiple interrupts and events.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10102161B2Microcomputer

Publication Date: 2018.10.16 RENESAS ELECTRONICS CORP

AI summary

A microcomputer includes: a central processing unit (CPU); a data transfer apparatus (DTC); and a storage apparatus (RAM). The data transfer apparatus includes a plurality of register files each including a mode register storing the transfer mode information, an address register to which the address information is transferred, and a status register (SR) representing information that specifies the transfer information set. The data transfer apparatus checks the information of the status register, to determine whether to use the transfer information set held in the register files or to read the transfer information set from the storage apparatus and to rewrite a prescribed one of the register files. The data transfer apparatus performs data transfer based on the transfer information set stored in one of the register files.