Processor Execution Unit Segmentation for Wiring Space Reduction

Solution Overview

Problem

The increase in execution units in processors leads to longer wire lengths and larger propagation delays due to increased wiring space, degrading performance, particularly in read paths from the register file to execution units.

Innovation Solution

A processing apparatus with two execution units that can perform computations on operands, one selectable between register and immediate values, and a control unit that determines which unit to use based on the instruction, reducing the number of input paths and wiring space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If more execution units are integrated in the same processor to enhance parallelism, then computation performance is improved, but wiring space increases leading to longer wire lengths and larger propagation delays

Engineering Contradiction:

Improvecomputation performanceVSAvoidwire length

Core Design Contradiction:

ProductivityVSLength of stationary object

Solution Approach 1:

The patent segments execution units into two distinct types: first execution units that perform computations on two register operands, and second execution units that perform computations on one register operand and one immediate value. This segmentation allows the processor to reduce the number of read paths from the register file, thereby reducing wiring space and propagation delays while maintaining computational performance through specialized units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by giving different input configurations to different execution units based on their specific function. First execution units have both inputs connected to the register file, while second execution units have one input connected to the register file and the other receiving immediate values directly. This localized optimization reduces overall wiring complexity while maintaining the ability to handle diverse computational tasks.

Inventive Principle:

Principle #3Local quality

2Productivity

If more execution units are integrated to enhance parallelism, then computation performance is improved, but the number of read paths from register file increases

Engineering Contradiction:

Improveparallelism of computationVSAvoidnumber of read paths

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments execution units into two distinct types: first execution units that perform computations on two register operands, and second execution units that perform computations on one register operand and one immediate value. This segmentation allows the processor to reduce the number of read paths from the register file, thereby reducing wiring space and propagation delays while maintaining computational performance through specialized units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates execution units with universal functionality by designing second execution units that can handle operations involving immediate values, which are commonly used in arithmetic and logical operations. This multi-functionality allows the processor to maintain high parallelism while reducing the number of dedicated read paths, as immediate values can be supplied through alternative routes rather than requiring additional register file connections.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9043581B2Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full

Publication Date: 2015.05.26 FUJITSU LTD

AI summary

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.