Vector Packed Multiplication for Dual Signed Unsigned Data
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Solution Overview
Problem
Current computer processors lack an efficient method for performing dual signed and unsigned multiplication of packed data elements, requiring multiple instructions and complicating digital signal processing operations.
Innovation Solution
The introduction of vector packed instructions, such as VPMULUDHHQ for unsigned multiplication and VPMULDHHQ for signed multiplication, allows for concurrent multiplication of packed data elements within a single instruction, simplifying the process and improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple separate instructions are used for signed and unsigned multiplication, then processing flexibility is maintained, but instruction count increases and processing efficiency decreases
Solution Approach 1:
The patent combines signed multiplication and unsigned multiplication operations into a single SIMD instruction that can process multiple packed data elements concurrently. The instruction uses a unified opcode structure that handles both signed and unsigned operations through different execution paths within the same instruction stream, eliminating the need for separate instructions for each operation type.
Solution Approach 2:
The multiplication instruction is designed with multi-functionality to handle both signed and unsigned packed data elements using the same instruction format. The instruction includes fields that can specify different operation types (signed/unsigned) and different data element sizes (16-bit, 32-bit, 64-bit), allowing a single instruction to perform multiple multiplication variants without requiring separate dedicated instructions for each case.
2Speed
If sequential multiply-accumulate operations are performed using multiple instructions, then operation accuracy is maintained, but execution time increases
Solution Approach 1:
The patent implements continuous useful action by enabling concurrent execution of multiple multiplication operations within a single instruction. The SIMD architecture allows parallel processing of multiple packed data elements (e.g., 4x16-bit, 2x32-bit, or 1x64-bit elements) simultaneously in one instruction cycle, eliminating the sequential execution delays that would occur with multiple separate instructions.
Solution Approach 2:
The patent transitions from scalar sequential operations to vector parallel operations by utilizing SIMD technology. This dimensional change allows the processor to handle multiple data elements in parallel across different lanes of the vector register, effectively converting a time-consuming sequential process into a spatially parallel operation that completes in a single instruction cycle.
Data Source
AI summary
An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed byte data elements; a second source register to store a second plurality of packed byte data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to concurrently multiply each of the packed byte data elements of the first plurality with a corresponding packed byte data element of the second plurality to generate a plurality of products; adder circuitry to add specified sets of the products to generate temporary results for each set of products; zero-extension or sign-extension circuitry to zero-extend or sign-extend the temporary result for each set to generate an extended temporary result for each set; accumulation circuitry to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and a destination register to store the plurality of final results as a plurality of packed data elements in specified data element positions.