Programmable Filter Processor Pipeline Parallelism
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Solution Overview
Problem
The increasing complexity and data quantity in engine control units pose challenges for real-time signal processing, as existing microchips struggle with parallelism and cost constraints, leading to inefficiencies in software-based signal processing.
Innovation Solution
A programmable filter processor with a logic unit, multiple pipeline stages, and controllable memory units that can be programmed via assembler instructions, allowing adaptation to various filtering algorithms and tasks, including processing of time stamps and data parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based signal processing is used in existing microchips, then cost is reduced and device complexity is lowered, but real-time processing capability and parallelism are insufficient
Solution Approach 1:
The processor is divided into multiple pipeline stages (fetch, decode, execute, memory access, write-back) that can operate simultaneously on different instructions. This segmentation enables parallel processing of multiple signal filtering tasks while maintaining a manageable device structure through modular architecture.
Solution Approach 2:
The processor implements dynamic instruction streaming where multiple instructions are fetched, decoded, and executed in overlapping time windows through the pipeline. This dynamic operation allows the system to adapt to varying signal processing demands in real-time while maintaining efficient resource utilization.
2Productivity
If multiple parallel controller structures are implemented, then real-time signal processing capability is improved, but cost increases
Solution Approach 1:
The processor implements a universal pipeline architecture that can execute multiple different filtering algorithms (moving average, exponential smoothing, median filtering) using the same hardware structure. This multi-functionality provides parallel processing capability for multiple signal streams without requiring separate dedicated hardware for each algorithm, thereby controlling cost.
Solution Approach 2:
The processor achieves different filtering behaviors by changing software parameters (filter coefficients, window sizes, sampling rates) rather than changing hardware configuration. This allows flexible adaptation to different signal processing requirements while maintaining a single cost-effective hardware platform.
3Adaptability or versatility
If a fixed-function processor is used, then device complexity is reduced, but adaptability to different filtering algorithms is limited
Solution Approach 1:
The processor transitions from static fixed-function to dynamic reconfigurable operation through pipelined instruction execution. The same hardware structure can be dynamically reconfigured via software to implement different filtering algorithms, providing adaptability without permanently increasing device complexity.
Solution Approach 2:
The processor uses software instructions to replicate and execute the same filtering logic multiple times in parallel pipeline stages. This allows a single algorithm implementation to be copied and executed concurrently for multiple signal streams, providing both adaptability and parallelism.
4Speed
If data processing and algorithm execution are performed sequentially, then device complexity is minimized, but processing speed and real-time capability deteriorate
Solution Approach 1:
The processing pipeline is segmented into five distinct stages (fetch, decode, execute, memory access, write-back) that operate simultaneously. Each stage processes a different instruction at the same time, multiplying the effective processing speed without requiring a proportionally complex increase in overall device structure.
Solution Approach 2:
Instructions are fetched and decoded in advance during earlier pipeline stages while later stages are executing previous instructions. This preliminary action ensures that data and control information are prepared before they are needed, enabling continuous high-speed processing without waiting for sequential completion of each operation.
Data Source
AI summary
A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit.