Bit-Line Discharge Timing for Read-While-Write Reliability
Solution Overview
Problem
Non-volatile semiconductor memory devices face reduced operational reliability and stability due to the coupling phenomenon between discharge operations of global write bit-lines and development operations of global read bit-lines during read-while-write operations, leading to differences in write and read speeds.
Innovation Solution
A method involving the discharge of global write bit-lines to ground voltage based on a write command, maintaining this voltage during a specific period, and discharging local bit-lines to ground voltage at designated timing points to prevent coupling between discharge and development operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a non-volatile semiconductor memory device performs read-while-write operation with paired global write bit-line and global read bit-line coupled to local bit-line, then the device can overcome the speed difference between write and read operations, but a coupling phenomenon occurs between discharge operation of global write bit-line and develop operation of global read bit-line leading to lower operation reliability and stability
Solution Approach 1:
The patent divides the bit-line discharge operation into two separate time periods: a first period for discharging the global write bit-line and a second period for discharging the local bit-line. This temporal segmentation prevents the coupling phenomenon between write discharge and read develop operations, allowing read-while-write operation to proceed reliably without interference between simultaneous write and read activities on coupled bit-lines.
Solution Approach 2:
The patent performs the discharge of the global write bit-line in advance during the first period before the local bit-line is discharged in the second period. This preliminary action ensures that when the read operation develops on the global read bit-line, the coupled global write bit-line is already discharged and stable, preventing coupling interference and enabling reliable read-while-write operation.
2Loss of energy
If global write bit-line and local bit-line are maintained in floating state before write command, then power consumption is reduced, but write operation timing becomes more complex
Solution Approach 1:
The patent implements a periodic timing scheme where bit-lines are discharged in distinct periods: the global write bit-line is discharged in the first period after the write command, and the local bit-line is discharged in the second period. This structured periodic action manages the complexity of timing control by establishing clear discharge sequences while maintaining power efficiency through floating state before discharge.
Data Source
AI summary
In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.