Bitline Leakage Detection via Extended Delay Circuits
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Solution Overview
Problem
Integrated circuits face read and write errors due to excessive bitline leakage in SRAM memory arrays, which can lead to costly burn-in testing, and existing methods do not effectively detect and address this issue during final testing.
Innovation Solution
Implementing extended delay circuits in bitline leakage tests during final testing to identify and potentially repair or replace defective bitlines, thereby reducing the need for burn-in testing by detecting excessive leakage before chip production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extended delay tests are implemented to detect bitline leakage, then detection capability is improved, but test time increases
Solution Approach 1:
The patent applies preliminary action by performing bitline leakage detection during the final test stage before chip production, rather than relying on costly burn-in testing later. The extended delay circuit is configured to detect leakage conditions before the chip is shipped, allowing early identification and replacement of defective bits.
Solution Approach 2:
The system uses self-service by implementing built-in self-test (BIST) functionality where the memory array tests itself for bitline leakage during normal operation. The test circuitry is integrated within the memory device, allowing autonomous detection without requiring external specialized equipment.
2Reliability
If burn-in testing is performed to ensure reliability, then reliability is improved, but production cost increases
Solution Approach 1:
The patent performs reliability testing in advance during the final test stage, identifying and replacing defective memory bits before production. This preliminary detection prevents defective chips from entering production, eliminating the need for costly post-production burn-in testing while maintaining high reliability.
Solution Approach 2:
The patent extracts and addresses the bitline leakage issue specifically by implementing targeted detection circuits and test methodologies that isolate this particular failure mode. By focusing on extracting and solving this specific reliability problem during final test, the patent avoids the need for comprehensive expensive burn-in testing.
3Productivity
If bitline leakage is not detected during final testing, then production proceeds efficiently, but read/write errors occur
Solution Approach 1:
The memory array performs self-testing for bitline leakage during final test using integrated BIST circuitry. This allows the system to automatically detect leakage conditions without requiring external specialized equipment, maintaining production efficiency while ensuring reliability through continuous self-monitoring.
Solution Approach 2:
The patent implements feedback mechanisms where test results from bitline leakage detection are used to control the replacement of defective memory bits. The test circuitry provides feedback signals that indicate when leakage is detected, triggering automated replacement procedures that maintain both production efficiency and product reliability.
Data Source
AI summary
An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.