Digital Storage TRIZ Cases

Non-linear current pulses drive resistance changes in resistive memory cells, resolving linear pulse unpredictability to improve write efficiency.

A shared data output control unit generates clock pulses to synchronize multiple data output units, reducing chip size and current consumption.

A write controlling circuit provides fixed or variable pulses to drive internal memory cells.

Calibration resistor circuit stabilizes reference resistance accuracy by comparing currents during read operations to reduce errors from process variations.

Segmented selection circuitry connects grouped bit lines to local drivers, reducing voltage stress on completed elements during simultaneous forming.

A semiconductor memory device advances word line enable timing using a block information signal without redundancy data.

A DDR Auto Scan controller generates and compares data streams to detect defects within system-on-chip memory.

Extended delay circuits float precharged bitlines longer to detect excessive leakage currents, identifying defective memory bits before final chip production.

A current mirror duplicates SRAM bit-line read current to power a ring oscillator for frequency-based sensing.

Dynamic sensing frequency adjustment resolves the trade-off between data retention reliability and power consumption in dynamic random access memory.

A variable resistance memory inspection method applies distinct voltage levels to identify short-circuit faults in bidirectional current steering elements.

A variable resistance memory device uses a current steering circuit to manage gate voltage and cell current for stable operation.

A 2T1C ferro-electric memory cell generates a local reference voltage using two distinct wordlines and a bit-level pulse scheme.

Local data line generation isolates sensing amplifiers from main input-output lines to reduce voltage usage.

Programmable impedance elements shadow dynamic storage to retain data without power, eliminating frequent refresh operations and reducing system complexity.

A synchronizer circuit coordinates signals between segmented CAMs, resolving timing mismatches and invalid combination detection.

A row hammer management circuit counts access frequencies in memory cell rows and updates count data via internal read-update-write operations.

Coupling a reference voltage to a sense amplifier input increases the differential signal detected across digit lines.

Segmented sense amplifier units amplify voltage differences in resistive memory cells to resolve the trade-off between non-volatility and data input speed.

A timing control circuit generates an internal strobe signal using a variable delay adjusted by temperature to latch data accurately.

Retrieve unprocessed data from an overflowing receive buffer to free memory space for new incoming information.

Diode-PFET switches adjust voltage drops on dummy bit lines to control signal development time, resolving read accuracy versus access speed trade-offs.

A semiconductor system staggers refresh operations across stacked chips to reduce peak current consumption.

A semiconductor memory chip die uses a second I/O pad to transmit via or differential signals based on stacking status.

Copying threshold voltage drift from phase change cells via a reference memory cell stabilizes reading accuracy without increasing latency.

A time-multiplexed bitcell architecture increases read-write ports using shared transistor networks.

A readout circuit applies distinct positive and negative voltage amplitudes to a memristor crossbar array.

A burn-in process fixes values in tail-region memory cells to expose them to stress while alternating other cells to alleviate stress.

A voltage disturb protection scheme disables a master oscillator to stop high voltage generation.

Series-connected tracking circuits emulate global and local variations to optimize word line pulse duration, reducing power consumption.

A pulse-shaped read current with a width under 8 nanoseconds detects data in magnetoresistive memory elements.

Segmenting power domains via selective bit line coupling resolves the trade-off between cell reliability and system power consumption.

Composite spin-orbit torque wiring uses insertion layers to lower electrical resistance, reducing writing voltage while maintaining spin injection efficiency.

External comparator logic de-asserts faulty row access and asserts redundant row access, improving yield without area penalties.

An over-drive circuit adjusts the VCCSA voltage level based on sense signals to prevent data flipping during bit line sensing operations.

Energy gradients in the buffer layer stabilize domain walls, preventing movement and ensuring data retention during high-speed writes.

Vertical MOS capacitors stack above power lines to increase decoupling capacitance without expanding chip area or layout complexity.

Applying a second voltage pulse with opposite polarity cancels threshold voltage drift, eliminating additional bias voltages and snap back detection circuitry.

An optical splitting module converts electrical clock and test signals into optical formats for distribution across multiple memory devices.

Cell transistors adjust interface states via hot-carrier injection to balance series resistance, resolving unequal distribution that reduces sensing margins.

Applying forward and reverse biases to a PN junction diode switches variable resistance memory states, resolving bidirectional current control complexity.

A memory controller uses latch sections and a comparison unit to identify frequently accessed addresses.

A nonvolatile memory device uses a resistance switching layer to change electrical conductivity based on light illumination.

Slope analysis of fail bit distributions during elevated temperature screening detects stuck bits in FRAM cells, preventing data retention failures.

Segmented ferroelectric capacitor architecture enables non-destructive data retrieval while reducing excessive voltage generation during write operations.

A dual-port SRAM cell uses a non-symmetric read port structure to enhance read current performance.

A driving method adjusts transistor resistance to stabilize read current in variable resistance memory elements.

Dual-sided pin placement relaxes tight routing constraints and reduces bitline loading capacitance without increasing circuit area.

A cross-point magnetoresistive random access memory array uses self-aligned patterning with dielectric spacers to define precise conductive line geometry.