Semiconductor Storage Device Bit Line Grouping for Forming

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Solution Overview

Problem

The existing methods for forming variable resistance elements in semiconductor storage devices are either time-consuming when done one by one or subject the elements to excessive voltage stress when done in bulk, leading to inefficiencies and potential damage.

Innovation Solution

A semiconductor storage device configuration that includes a selection circuitry system allowing for the precharging and controlled connection of bit lines to global and local lines, enabling simultaneous forming of multiple memory cells with reduced voltage stress by using accumulated charges, thereby optimizing the forming process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If forming of variable resistance elements is performed one by one, then voltage stress on completed elements is reduced, but forming time becomes very long

Engineering Contradiction:
Improvevoltage stress on completed elementsVSAvoidforming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The bit lines are divided into multiple groups, with each group containing a specific number of bit lines. Selection circuits selectively connect groups of bit lines to local lines and global lines, enabling controlled parallel forming operations. This segmentation allows multiple variable resistance elements to be formed simultaneously while managing voltage stress through group-based control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The selection circuits dynamically connect and disconnect bit line groups to local lines and global lines based on forming requirements. During forming operations, selected bit line groups are connected to apply forming voltage, while other groups remain disconnected to avoid excessive voltage stress. This dynamic connectivity enables flexible control over parallel forming operations.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If forming of multiple variable resistance elements is performed simultaneously, then forming time is reduced, but excessive voltage stress is applied to completed elements

Engineering Contradiction:
Improveforming timeVSAvoidvoltage stress on completed elements
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

Bit lines are organized into multiple groups that can be independently controlled. Selection circuits enable specific groups to be activated for forming while other groups remain inactive or are connected to different voltage levels. This segmentation allows simultaneous forming of multiple elements without subjecting all elements to maximum voltage stress continuously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different bit line groups receive different voltage conditions based on their forming status. Completed elements are connected to local lines with reduced or zero voltage stress, while elements needing forming receive full forming voltage through selected bit line groups. This local differentiation of voltage conditions protects completed elements while maintaining forming efficiency.

Inventive Principle:
Principle #3Local quality

3Productivity

If voltage is continuously applied to perform simultaneous forming, then forming speed increases, but load on bit line driver increases

Engineering Contradiction:
Improveforming speedVSAvoidload on bit line driver
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The bit line driver's load is distributed across multiple selectable groups of bit lines. At any given time, only selected groups are connected to the driver for active forming operations, while other groups are disconnected or connected to different voltage sources. This segmentation reduces the instantaneous current demand on the bit line driver while maintaining high forming throughput through parallel operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The selection circuits dynamically reconfigure which bit line groups are connected to the bit line driver based on forming progress and requirements. As elements complete forming, their bit lines are switched to different configurations that reduce driver load. This dynamic reconfiguration maintains high forming speed while optimizing power consumption and driver utilization.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11328770B2Semiconductor storage device
Publication Date: 2022.05.10 KIOXIA CORP
  • US11328770B2 patent drawing
  • US11328770B2 patent drawing
  • US11328770B2 patent drawing

AI summary

A memory includes first-lines, second-lines, and memory cells. Third-lines are provided to respectively correspond to groups each comprising m (m≥2) lines of the first-lines. A first selector selects a certain one of the first-lines from the groups and to connect the selected first-lines to the third-lines corresponding to the groups. Fourth-lines correspond to the third-lines. A second selector selects one of the third-lines and to connect the fourth-line to the selected third-line. A third selector selects a certain one of the second-lines. A first driver applied a voltage to the fourth-line. A second driver is connected to the third selector. The first driver charges the third-line corresponding to the first-line selected from the groups via the fourth-line. The first and second selectors bring the selected first-line and the third-line corresponding the first-line to an electrically floating state. The second driver applies a voltage to the selected second-line.