DDR Memory Interface Testing in SoC via Background Scan
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional defect mapping processes in memory devices monopolize the memory during testing, preventing their use during runtime, and existing methods for testing System-on-Chip (SoC) with double data rate (DDR) memory interfaces face challenges in at-speed testing, leading to increased defective parts per million and debug time, thereby increasing production costs.
Innovation Solution
A method and system for testing a DDR memory interface within a System-on-Chip (SoC) that generates a data stream, writes it to internal memory, reads it back, and compares the original with the read data using a DDR Auto Scan (DAS) controller, which operates in the background without interfering with other processes, allowing for defect detection and testing without monopolizing the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional defect mapping processes are used to test memory devices, then defects can be detected and mapped, but the memory device is monopolized during testing and cannot be used during runtime
Solution Approach 1:
The patent segments the memory testing function by introducing a separate defect mapping process that operates independently from normal memory operations. The defect mapping is performed as a background process that does not block or monopolize the main memory device, allowing simultaneous access for both testing and operational purposes.
Solution Approach 2:
The patent introduces an intermediary defect mapping process that acts as a mediator between the memory device and the testing requirements. This intermediary process handles defect detection and mapping without interfering with the primary memory operations, enabling non-intrusive testing.
2Speed
If automated test equipment is used to test SoC at high speeds, then testing can be performed, but the complexity of at-speed testing increases defective parts per million and debug time
Solution Approach 1:
The patent implements self-service testing capabilities within the SoC itself, where the system tests its own DDR memory interface using internal resources. The SoC generates test patterns, performs the testing, and detects defects using its own processing units and memory structures, eliminating the need for complex external automated test equipment and reducing debug complexity.
Solution Approach 2:
The patent merges the testing functions with the normal operational functions of the SoC. The defect mapping process is integrated into the existing memory controller and processing units, combining testing operations with data processing operations to simplify the overall testing architecture and reduce the complexity associated with separate testing systems.
Data Source
AI summary
A method of testing a double data rate (DDR) memory interface within a System-on-chip (SoC). The method comprises generating a data stream within the SoC and writing the data stream to an internal memory within the SoC via the DDR memory interface. The method further comprises reading the data stream from the internal memory within the SoC and comparing the data stream generated within the SoC with the data stream read from the internal memory within the SoC.