Variable Resistance Memory Device with Current Steering Circuit
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Solution Overview
Problem
Variable resistance nonvolatile memory devices face challenges in maintaining stable resistance change operations over a large number of rewriting cycles, with conventional methods experiencing issues such as high resistance state fixation and reduced writing speed due to verification operations.
Innovation Solution
A variable resistance nonvolatile memory device design incorporating a nonvolatile memory element with a variable resistance layer and an NMOS transistor, along with a current steering circuit and switch circuits, allows for controlled resistance changes by managing current and voltage levels, ensuring stable operation across multiple cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional writing methods are used to change resistance state, then resistance change can be achieved, but stable operation over large number of rewriting cycles cannot be maintained
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level (VBL = VDD - Vth or higher) before the writing operation. This preliminary voltage setup ensures that when the word line is activated, the memory element immediately experiences the correct voltage differential for reliable resistance state change, regardless of previous cycle variations. This pre-conditioning of the circuit state before the actual write operation enables stable operation over 100,000 rewriting cycles.
2Measurement precision
If verification writing is performed to ensure correct resistance state, then writing accuracy is improved, but writing speed is reduced
Solution Approach 1:
The patent implements self-service by designing the memory element and circuit to inherently indicate the resistance state through current flow characteristics during the writing operation itself. The memory element's own electrical response (current magnitude and direction) serves as the verification mechanism, eliminating the need for separate verification write cycles. This allows the system to achieve both high writing accuracy and maintained writing speed.
3Manufacturing precision
If current steering circuit is used to control current flow, then resistance state regulation is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the bit line to serve multiple functions: it acts as both a voltage supply line (pre-charged to VDD - Vth) and a current sensing line (measuring the write current IW). The same bit line infrastructure is used for both establishing the voltage condition for resistance change and for verifying the operation outcome through current measurement. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while maintaining precise resistance state regulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables stable resistance change operations for up to 100,000 cycles with minimal variation in cell current distribution, reducing the need for verification writing and maintaining high writing speed.
Implementation Method 1
a variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer between the first electrode and the second electrode, and changes reversibly between a low resistance state and a high resistance state according to an applied electrical signal
Data Source
AI summary
A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.