Memory Controller Target Refresh Logic for Row Disturbance
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Solution Overview
Problem
Volatile memory devices, such as DRAM, face data loss due to leakage currents and the row disturbance phenomenon, where frequently accessed word lines interfere with adjacent word lines, causing data damage and loss.
Innovation Solution
A memory system with a memory controller that detects frequently accessed word lines and performs a target refresh operation on adjacent word lines, using latch sections to store target and recent addresses, a comparison unit to identify matches, and a counting section to update addresses and perform refresh operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a specific word line is repeatedly activated, then the access speed and operational efficiency are improved, but the data of memory cells electrically coupled to adjacent word lines may be damaged due to row disturbance phenomenon
Solution Approach 1:
The patent performs a refresh operation on adjacent word lines in advance before the row disturbance phenomenon can cause data loss. When a word line is activated multiple times, the system proactively refreshes the adjacent word lines to prevent potential data corruption, rather than waiting for actual data loss to occur.
Solution Approach 2:
The patent applies a counteracting refresh operation to neutralize the harmful coupling effect. By activating adjacent word lines with a refresh operation, the system creates an opposing electrical effect that counteracts the coupling-induced charge leakage, thereby preventing data damage before it can occur.
2Adaptability or versatility
If the interval between adjacent word lines is reduced to increase integration density, then the memory device integration is improved, but the coupling effect between adjacent word lines increases causing more row disturbance
Solution Approach 1:
The patent converts the harmful coupling effect into a beneficial mechanism by using it as a detection criterion. The increased coupling effect in high-density memory is leveraged to identify which word lines require refresh operations, transforming the previously harmful phenomenon into a useful indicator for targeted refresh operations that maintain data integrity in high-density configurations.
3Reliability
If a refresh operation is performed on all word lines periodically, then data retention is improved, but the overhead and power consumption of refresh operations increases
Solution Approach 1:
The patent applies refresh operations selectively to specific adjacent word lines based on their proximity to frequently accessed word lines, rather than uniformly refreshing all word lines. This localized approach concentrates refresh resources where the coupling effect is most likely to cause damage, reducing overall refresh overhead and power consumption while maintaining data integrity in affected regions.
Solution Approach 2:
The patent performs refresh operations on a subset of word lines (specifically those adjacent to frequently accessed lines) rather than all word lines. This partial action is sufficient to prevent row disturbance phenomenon in the most vulnerable regions, achieving adequate data protection with reduced refresh overhead compared to a complete refresh of all word lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces data loss and interference between word lines by performing targeted refresh operations, enhancing data retention and reducing the overhead of memory device refresh operations.
Implementation Method 1
a comparison unit to compare the input address with target addresses and recent input addresses respectively stored in the first and second latch sections
Implementation Method 2
a counting section to increase a count corresponding to a matched recent input address stored in the second latch section in response to the resultant signal
Implementation Method 3
a control unit to update the input address to the second latch section in response to the resultant signal when a value of the count is smaller than a reference value
Implementation Method 4
the initial amount of charge stored in the capacitor of a memory cell may decrease over time due to a leakage current caused by a PN junction of a MOS type transistor
Implementation Method 5
a capacitor for storing data in the form of a charge
Implementation Method 6
the interval between adjacent word lines in the memory device is reduced, which may result in an increase of a coupling effect between adjacent word lines
Implementation Method 7
A leakage current and a parasitic current caused by repeated access to a specific word line may drift data corresponding to non-accessed word lines physically adjacent to the specific word line
Data Source
AI summary
A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.