Dual-Port SRAM Cell with Non-Symmetric FinFET Read Port
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In deep sub-micron integrated circuit technology, the thin style dual-port SRAM cell structure with a long word line to short bit line ratio greater than 3.5 faces issues such as data node leakage, device matching problems, and current crowding, particularly when used in fin field effect transistors with long contact structures, limiting performance.
Innovation Solution
A dual-port SRAM cell design is implemented with a non-symmetric structure for the read port portion, featuring a greater number of fin field-effect transistors (FinFETs) in the pull-down devices and a lesser number in the pass-gate devices, along with different fin active region configurations and space settings to reduce bit line capacitance and enhance read current performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a thin style SRAM cell structure with short bit line is used, then metal layer coupling capacitance is reduced, but coupling capacitances associated with the front end of line (active regions and gates) and the middle end of line (contacts) are not improved, and long word line causes data node leakage and current crowding
Solution Approach 1:
The bit line is segmented into multiple segments (first bit line segment, second bit line segment, third bit line segment) with different length configurations. The first and second bit line segments are shorter to reduce coupling capacitance, while the third bit line segment is longer to reduce data node leakage and current crowding effects.
Solution Approach 2:
Different portions of the bit line are given different local characteristics - the first and second bit line segments have shorter lengths optimized for coupling capacitance reduction, while the third bit line segment has a longer length optimized for reducing data node leakage and current crowding, allowing each section to be optimized for its specific function.
2Power
If a non-symmetric structure with greater number of FinFETs in pull-down devices is used, then read current performance is enhanced, but device complexity increases
Solution Approach 1:
The pull-down devices are configured with a greater number of FinFETs compared to pass-gate devices, creating a non-symmetric structure where different device types have different FinFET counts optimized for their specific functions - pull-down devices prioritize read current drive capability while pass-gate devices maintain simpler structures.
Data Source
AI summary
A dual port static random access memory cell includes a write port portion and a read port portion. The write port further includes a WPU1 and a WPU2; a WPD1 and a WPD2; and a WPG1 and a WPG2. The WPU1, WPU2, WPD1 and WPD2 are configured to form two cross-coupled inverters for data storage, wherein the WPG1 and WPG2 are connected to the two cross-coupled inverters for writing. The read port portion further includes a read pull down device (RPD) and a read pass gate device (RPG) connected to the two cross-coupled inverters for reading. Each of the WPU1 and WPU2 includes a single FinFET. Each of the WPD1, WPD2, WPG1, WPG2, RPD and RPG includes multiple FinFETs. The WPD1, WPD2, WPG1 and WPG2 include a same number of FinFETs. The RPD includes a number of FinFETs greater than a number of FinFETs in the RPG.