External Comparator Logic for Memory Redundancy

The patent divides the memory array into multiple banks, with each bank having its own independent redundancy circuitry and comparator logic. This segmentation allows each bank to handle failures independently, improving yield without requiring global redundancy that would increase overall area and complexity. The segmentation principle is applied by creating separate redundancy paths for different row groups.

The patent introduces comparator logic as an intermediary component that sits between the address input and the memory array. This comparator logic compares incoming addresses against stored faulty row addresses and redirects access away from defective rows to redundant rows. The intermediary comparator mechanism enables intelligent failure handling without requiring extensive redundant circuitry throughout the entire memory structure.

The patent designs the comparator logic and redundancy circuitry to serve multiple functions: they not only handle row failures but also provide address translation and can be shared across multiple memory banks. This multi-functionality reduces the need for dedicated redundancy circuitry in each bank, thereby reducing overall area occupancy while maintaining comprehensive failure handling capability.

The patent implements a mechanism where faulty rows are identified and discarded from normal operation, but their functionality is recovered by redirecting accesses to redundant rows. The comparator logic stores the addresses of faulty rows and automatically redirects access patterns to use redundant rows, effectively recovering the lost capacity without adding permanent redundant storage for every possible failure scenario.

The patent pre-populates the comparator logic with addresses of known faulty rows before normal memory operation begins. This preliminary action allows the comparator to instantly recognize and redirect accesses to faulty rows without performing complex comparisons during normal operation, thereby minimizing performance penalty while maintaining reliable access control.

The patent implements a simplified copy of the address comparison function within the comparator logic, rather than using the full memory access path. The comparator creates a simplified decision path that copies only the essential address matching functionality, allowing fast identification of faulty row accesses without going through the complete memory access sequence, thus reducing performance impact.