Staggered Refresh Control for Stacked Semiconductor Chips
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Solution Overview
Problem
In semiconductor memory devices, the peak current increases when multiple banks activate word lines simultaneously, and as the integration of semiconductor devices improves, the scaling-down method has reached its technical limit, leading to challenges in managing peak current and charge pump area requirements in stacked semiconductor packages.
Innovation Solution
A semiconductor system and method that control the refresh operation of stacked chips by using a master chip to provide refresh signals and discrimination signals to slave chips, allowing each slave chip to perform refresh operations at different timings through a delay control circuit and end signal generation circuit, thereby reducing peak current and optimizing power supply usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple banks of stacked semiconductor chips perform refresh operation simultaneously, then the refresh operation is completed efficiently, but the peak current increases
Solution Approach 1:
The patent divides the stacked semiconductor chips into multiple groups, where each group performs refresh operations at different time intervals. This segmentation of the refresh operation across time groups prevents simultaneous activation of all banks, thereby reducing peak current while maintaining overall refresh efficiency
Solution Approach 2:
The patent implements periodic refresh operations where different groups of banks are activated at different periodic intervals. By controlling the timing of word line activations in a periodic manner across multiple groups, the system reduces instantaneous current demand while ensuring all memory cells are refreshed within acceptable time frames
2Quantity of substance
If the number of banks in stacked semiconductor chip package increases, then the memory capacity increases, but the peak current and charge pump area increase
Solution Approach 1:
The patent segments the large number of banks into multiple smaller groups that operate independently at different times. This allows the system to accommodate a high total number of banks for increased memory capacity while controlling peak current by activating only a subset of banks during each refresh cycle
Solution Approach 2:
The patent introduces dynamic control of bank activation timing, where the refresh operation of different bank groups is staggered in time. This dynamic timing control allows the system to scale up memory capacity without linearly increasing peak current demands, as not all banks are activated simultaneously
3Quantity of substance
If the number of banks in stacked semiconductor chip package increases, then the memory capacity increases, but the charge pump area increases
Solution Approach 1:
The patent divides the charge pump functionality across multiple groups corresponding to different bank groups. Each charge pump serves a specific group of banks activated at different times, allowing the total charge pump area to be distributed rather than concentrated, thus reducing the area required per charge pump while maintaining support for high memory capacity
Data Source
AI summary
A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.