Semiconductor Memory Chip Die I/O Pad Mode Switching

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Solution Overview

Problem

Next-generation DRAMs require optimization for mobile devices with smaller sizes and lower power consumption, necessitating improved I/O signaling and signal integration to enhance operation speed and reliability.

Innovation Solution

A semiconductor memory device with a chip die that selectively uses a dummy pad for I/O operations, determining whether stacked chip dies are present to perform either via or differential I/O operations, increasing integration and reliability through a Through Silicon Via (TSV) connection and a detect-signal generator for operation mode determination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a dummy pad is provided for I/O operations of other chip dies, then the chip die can support stacked configurations, but the chip die occupies additional area and reduces integration flexibility when stacking is not used

Engineering Contradiction:
Improvestacked configuration supportVSAvoidchip die area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The second I/O pad is designed to perform multiple functions: it serves as a via I/O pad when another chip die is stacked on top, and as a differential I/O pad when no chip die is stacked. This multi-functionality allows the chip die to adapt to different stacking configurations without requiring additional dedicated pads, thereby resolving the area overhead problem while maintaining versatility

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The chip die dynamically configures the function of the second I/O pad based on whether another chip die is detected during operation. The I/O driver selectively operates in via mode or differential mode according to the stacking status, allowing the system to optimize its configuration in real-time rather than being fixed to a single mode

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If the chip die is configured to perform both via I/O and differential I/O operations, then the I/O signaling flexibility is improved, but the device complexity increases due to additional control mechanisms

Engineering Contradiction:
ImproveI/O signaling flexibilityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system determines the stacking configuration in advance during initialization or power-up, before normal I/O operations begin. The detect-signal generator and controller establish the operational mode (via or differential) beforehand, allowing the I/O driver to operate in a predetermined mode without requiring complex real-time switching mechanisms during data transmission

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A detect-signal generator and controller are introduced as intermediary components that automatically determine the stacking status and generate appropriate operation mode signals. These intermediaries simplify the control logic by centralizing the decision-making process, rather than requiring complex distributed control across multiple I/O pads

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If a detect-signal generator and controller are added to determine stacking status, then the operation mode selection accuracy is improved, but the device complexity and power consumption increase

Engineering Contradiction:
Improvestacking status detection accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The detect-signal generator operates periodically or at specific intervals (such as during power-up or initialization) rather than continuously. This periodic operation allows the system to accurately determine stacking status when needed while minimizing power consumption during normal operation, as the detection mechanism is activated only when configuration information needs to be refreshed or established

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8982599B2Chip die and semiconductor memory device including the same
Publication Date: 2015.03.17 SK HYNIX INC
  • US8982599B2 patent drawing
  • US8982599B2 patent drawing
  • US8982599B2 patent drawing

AI summary

A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.