Memory Circuit Bit Line Voltage Domain Segmentation
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Solution Overview
Problem
Memory circuits face challenges in efficiently managing different power voltage levels between memory arrays and other circuits, leading to performance limitations and increased power consumption.
Innovation Solution
A memory circuit design that includes a bit line, a power node with a memory domain power voltage level, a reference node with a reference voltage level, and pass gates and drivers that selectively couple the bit line to these nodes based on distinct voltage levels, allowing for reliable operation and reduced power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory array operates at a higher power voltage level to support reliable memory cell functioning, then reliability is improved, but power consumption increases
Solution Approach 1:
The circuit is divided into two distinct power domains: a first power domain operating at a higher voltage level for the memory array to ensure reliable memory cell functioning, and a second power domain operating at a lower voltage level for surrounding circuits to reduce power consumption. This segmentation allows each domain to operate independently at its optimal voltage level.
Solution Approach 2:
Different voltage levels are applied to different parts of the circuit based on their specific requirements. The memory array receives a higher voltage level (VDD1) for reliable operation, while other circuits operate at a lower voltage level (VDD2), optimizing both reliability and power efficiency locally throughout the system.
2Productivity
If multiple power domains are implemented to enable separate circuit performance features, then overall circuit performance is improved, but device complexity increases
Solution Approach 1:
Pass gates are introduced as intermediary components to selectively couple bit lines to either the first power node (VDD1) or the second power node (VDD2) based on control signals. These pass gates act as mediators that manage the interaction between different power domains, enabling flexible voltage selection without requiring complex direct control mechanisms.
Solution Approach 2:
The circuit employs dynamic voltage selection where the voltage level applied to bit lines can be changed in real-time based on operational requirements. The pass gates are controlled by control signals that dynamically switch between connecting to VDD1 or VDD2, allowing the system to adapt voltage levels during different operational phases such as write operations or normal operation.
3Device complexity
If a single power voltage level is used for all circuits, then device complexity is reduced, but overall circuit performance is limited
Solution Approach 1:
The bit line interface is designed with multi-functionality to operate with multiple voltage levels. The same bit line infrastructure can be selectively coupled to either the first power node or the second power node through pass gates, allowing the system to universally support both high-voltage memory operations and low-voltage circuit operations without requiring separate dedicated lines for each function.
Data Source
AI summary
A circuit includes a bit line, a power node having a first power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bit line and the power node, and a driver coupled between the bit line and the reference node. The pass gate couples the bit line to the power node responsive to a first signal, and the driver couples the bit line to the reference node responsive to a second signal. The first signal is based on the first power voltage level, and the second signal is based on a second power voltage level between the reference voltage level and the first power voltage level.