Double-Pitch Memory Layout for Pin Pitch and Routing
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Solution Overview
Problem
The tight pitches of I/O pins in memory circuit layouts lead to difficulties in routing and increased loading capacitances, reducing the read/write speed of memory circuits while occupying significant area and power.
Innovation Solution
The double-pitch layout technique rearranges the memory circuit layout by grouping M×N arrays of one-bit memory cells into N/2 two-column pairs, mirroring the layout of each column, allowing I/O circuits to be placed on both sides of the array, effectively increasing the pitch of I/O pins to twice that of one-bit memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pitch of I/O pins is reduced to save area and fabrication costs, then the memory circuit area is reduced, but the routing difficulty increases and loading capacitance increases
Solution Approach 1:
The patent transitions from a single-sided I/O pin arrangement to a dual-sided arrangement, utilizing both sides of the memory cell array for I/O pin placement. This dimensional change in layout strategy allows pins to be distributed across two sides rather than crowded on one side, reducing pitch and routing complexity while maintaining area efficiency
Solution Approach 2:
The memory cell array is segmented into two distinct groups: first column memory cells and second column memory cells. Each group has its I/O pins located on opposite sides of the array, creating separate I/O access paths that reduce routing congestion and loading capacitance compared to a unified single-sided pin arrangement
2Area of stationary object
If the pitch of I/O pins is reduced to save area and fabrication costs, then the memory circuit area is reduced, but the read/write speed decreases due to larger loading capacitances
Solution Approach 1:
The I/O pin population is segmented into two separate groups located on opposite sides of the memory array. This segmentation distributes the total loading capacitance across two separate groups rather than concentrating it on one side, reducing the capacitance burden on individual pins and improving read/write speed while maintaining compact area
Solution Approach 2:
By utilizing the dual-sided arrangement, the patent effectively distributes I/O pins across two spatial dimensions (both sides of the array) rather than concentrating them on one side. This dimensional distribution reduces the effective loading capacitance per pin group, enabling faster read/write operations without increasing overall circuit area
3Area of stationary object
If tight pitch I/O pins are used, then area is saved, but the layout complexity and routing difficulty increase
Solution Approach 1:
The patent segments the memory array into two distinct column groups with I/O pins on opposite sides, creating a more regular and modular layout pattern. This segmentation simplifies the overall layout complexity compared to traditional tight-pitch single-sided arrangements by establishing clear spatial separation and organized routing paths
Solution Approach 2:
The dual-sided pin arrangement introduces a new spatial dimension for I/O access, transforming the layout from a single-sided planar arrangement to a distributed bidirectional configuration. This dimensional change simplifies routing by providing multiple access directions and reducing the complexity of interconnect patterns
Data Source
AI summary
Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.