Semiconductor Memory Word Line Driving Timing Control
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Solution Overview
Problem
In semiconductor memory devices, the RAS to CAS delay (tRCD) is exacerbated by the late enabling of word lines due to the presence of redundancy, leading to signal collisions and inefficiencies in determining which word line to enable.
Innovation Solution
A semiconductor memory device that advances the enable timing of word lines by using a block signal without redundancy information, incorporating a control signal generator, driving control signal generator, and main/sub word line driving controller to generate and control driving enable signals, thereby optimizing the timing of word line activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fuse box is used to determine whether a normal word line or a redundant word line will be enabled, then reliability is improved, but RAS to CAS delay increases
Solution Approach 1:
The patent applies preliminary action by generating a block signal before the normal word line enable signal. The block signal is generated in advance based on address decoding, and then used to control the enabling of word lines. This preliminary generation of the block signal allows the system to prepare the word line selection logic before the actual word line enabling occurs, thereby reducing the overall delay while maintaining reliability through the fuse box mechanism.
2Device complexity
If the normal word line enable signal is generated after the block signal, then device complexity is reduced, but word line enabling timing is delayed
Solution Approach 1:
The block signal is generated preliminarily before the normal word line enable signal. This preliminary generation of the block signal allows the enabling logic to be simplified while still achieving timely word line activation. The block signal serves as an intermediate control that prepares the system state before the final word line enable occurs.
Solution Approach 2:
The block signal acts as an intermediary between the address decoding and the word line enabling. It mediates the control logic by first establishing the block selection state, which then influences the timing and logic of the normal word line enable signal generation. This intermediary approach simplifies the overall control logic while maintaining proper timing.
3Adaptability or versatility
If the word line control signal is generated using redundancy information, then adaptability is improved, but signal collision risk increases
Solution Approach 1:
The block signal is generated preliminarily before the normal word line enable signal, establishing the selection state in advance. This preliminary action ensures that the word line control logic has sufficient time to properly sequence the enabling signals, preventing collisions while maintaining the adaptability to handle both normal and redundant word line scenarios through the fuse box mechanism.
Data Source
AI summary
A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.