Self-Aligned MRAM Array Patterning via Dielectric Spacers
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Solution Overview
Problem
Current magnetic memory devices, particularly cross-point MRAM arrays, face challenges in efficiently manufacturing and optimizing the structure of spin-transfer torque (STT) and spin-orbit-torque (SOT) MRAM cells, which affect data storage and retrieval efficiency.
Innovation Solution
The development of a memory array structure comprising first and second electrically conductive lines, selector-containing pillar structures, and magnetic tunnel junction (MTJ) pillar structures, with specific patterning and dielectric spacer formations to create a precise and efficient array configuration for MRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used for MRAM arrays, then manufacturing process is simpler, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
The patent applies preliminary action by forming mandrel structures and dielectric spacers before final patterning of the MTJ array. The dielectric spacers are deposited and patterned in advance to define precise pitch relationships, which then guide subsequent self-aligned patterning steps. This preliminary structure formation enables high precision alignment without requiring complex real-time alignment processes.
Solution Approach 2:
The patent uses dielectric spacers as intermediary structures that mediate between the mandrel patterns and the final MTJ electrode patterns. These spacers act as self-aligned masks and structural guides, transferring the pattern from the mandrel layer to the conductive layers with high fidelity. The intermediary spacer layer enables precise pitch multiplication and alignment without direct lithographic patterning of the final structures.
2Quantity of substance
If pitch multiplication is implemented to increase array density, then data storage capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements pitch multiplication using a nested structure where dielectric spacers are formed around mandrel structures, and then additional spacers are formed around the first spacers. This nested spacer formation process multiplies the pitch by factors of 2 or 4 while maintaining precise spacing control. Each nesting level doubles the pitch, enabling high array density with controlled manufacturing precision through self-aligned processes.
3Adaptability or versatility
If variable width conductive lines are used for selector elements, then device functionality improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by forming conductive lines with variable widths that are optimized for specific functional regions. The selector electrode lines have different widths in different segments to provide appropriate resistance and current characteristics for selection operations. This local variation in geometry is achieved through selective etching or deposition processes that modify the conductive line dimensions in specific areas while maintaining simplicity in the overall fabrication flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the manufacturing efficiency and data storage capabilities of MRAM cells by optimizing the alignment and spacing of conductive lines and MTJ structures, improving the overall performance and reliability of the memory device.
Implementation Method 1
Spin-transfer torque (STT) refers to an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve is modified by a spin-polarized current
Implementation Method 2
Spin-orbit-torque (SOT) MRAM devices use switching of magnetization direction of a free magnetic layer by injection of an in-plane current in an adjacent conductive layer, which is referred to as a spin-orbit-torque (SOT) layer
Implementation Method 3
A resistance differential of a magnetic tunnel junction between different magnetization states of the free layer can be employed to store data within the magnetoresistive random access memory (MRAM) cell
Data Source
AI summary
A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.