Memory Disturb Protection Circuit Using Oscillator Control
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Solution Overview
Problem
Semiconductor memory devices face issues with erroneous logic signals and bit cell disturbances due to low power supply voltages, leading to unreliable operation, as the high voltage power supply can inadvertently alter the electrical characteristics of memory cells.
Innovation Solution
A voltage disturb protection scheme is implemented using multiple charge pumps and a shared master oscillator, where a Low Voltage Indicator signal disables the master oscillator when the Logic Power Domain voltage falls below a threshold, preventing high voltage coupling to memory bit cells and ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the logic power supply voltage falls below the critical value, then erroneous logic signals are generated, but the high voltage power supply continues to operate and alter memory cell characteristics
Solution Approach 1:
The patent applies preliminary anti-action by detecting the low voltage condition in the logic power domain before erroneous logic signals can cause harm, and preemptively disabling the master oscillator to prevent high voltage generation. The low voltage indicator circuit detects when VDD2 falls below VTH2 and asserts a signal that disables the master oscillator before incorrect logic values can be generated that would trigger high voltage memory operations.
Solution Approach 2:
The patent uses an intermediary approach by introducing a master oscillator control circuit that acts as a mediator between the logic power domain and the high voltage generation system. This control circuit receives the low voltage indicator signal and translates it into a disable signal for the master oscillator, creating an intermediate control layer that prevents direct coupling of high voltage to memory cells when logic operations are unreliable.
2Device complexity
If a single master oscillator is shared by multiple charge pumps, then device complexity is reduced, but the risk of high voltage memory disturb increases when logic power is insufficient
Solution Approach 1:
The patent implements feedback by creating a closed-loop control system where the master oscillator control circuit continuously monitors the logic power domain voltage level through the low voltage indicator and adjusts the master oscillator operation accordingly. When the voltage drops below the threshold, the feedback signal disables the oscillator; when voltage recovers, the oscillator is re-enabled, creating a self-regulating system that maintains reliability without complex manual intervention.
3Adaptability or versatility
If high voltage is generated for memory programming and erasing, then memory operation capability is improved, but memory cell electrical characteristics are altered when logic power is low
Solution Approach 1:
The patent applies preliminary action by ensuring that the logic power domain voltage is verified to be above the critical threshold before allowing the master oscillator to generate clocks that drive charge pumps for high voltage generation. This preliminary voltage check prevents memory programming or erasing operations from occurring under conditions where logic control signals may be erroneous, thereby protecting memory cell electrical characteristics from unintended alteration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents high voltage memory disturb, ensuring reliable data storage by selectively disabling the charge pumps and maintaining accurate voltage levels, thus avoiding soft hot carrier injection and bit cell disturbances.
Implementation Method 1
multiple charge pumps, wherein each of the multiple charge pumps is implemented as a voltage multiplier circuit
Implementation Method 2
A low voltage indicator circuit detects when a voltage level of the logic power domain falls below a predetermined minimum voltage value
Data Source
AI summary
A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator oscillating. The higher voltages are used to operate the memory array. Operation of the oscillator is controlled with the memory control logic when the logic power domain is at least at a first level or value. The oscillator is disabled when the logic power domain is below the first level. The disabling of the oscillator has the effect of preventing generation of the higher voltages. This facilitates preventing the higher voltages from reaching the memory array when they may not be properly controlled.