DRAM Row Hammer Management Circuit Using Precharge Command
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face challenges in defending against row hammer attacks, which lead to data loss due to frequent access of certain memory cell rows, causing adjacent cells to lose charges, and existing solutions require additional commands and increase power consumption.
Innovation Solution
A semiconductor memory device with a row hammer management circuit that counts access frequencies and performs internal read-update-write operations based on a precharge command, randomizing count data to prevent overflow and maintain performance without additional dedicated commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated command is used to update count data for row hammer defense, then security against row hammer attacks is improved, but device complexity and power consumption increase
Solution Approach 1:
The precharge command is given multiple functions: it performs both its traditional function of precharging memory rows and an additional function of triggering count data updates for row hammer defense. This eliminates the need for a dedicated count update command while maintaining security functionality.
Solution Approach 2:
The count update operation is merged with the precharge operation. Both functions are executed during the same command cycle, reducing the total number of commands needed and simplifying the command structure while maintaining both precharging and security update functionalities.
2Reliability
If a dedicated command is used to update count data for row hammer defense, then security against row hammer attacks is improved, but power consumption increases
Solution Approach 1:
The precharge command is given multiple functions: it performs both its traditional function of precharging memory rows and an additional function of triggering count data updates for row hammer defense. This eliminates the need for a dedicated count update command while maintaining security functionality.
Solution Approach 2:
The count update operation is merged with the precharge operation. Both functions are executed during the same command cycle, reducing the total number of commands needed and simplifying the command structure while maintaining both precharging and security update functionalities.
3Reliability
If access count is increased to detect row hammer attacks, then security detection capability is improved, but performance degradation occurs due to frequent refresh operations
Solution Approach 1:
The system performs preliminary actions by updating count data during precharge operations before potential row hammer attacks can cause damage. This proactive counting allows the system to detect and respond to attack patterns while using existing command overhead efficiently.
Solution Approach 2:
The system implements feedback by monitoring access counts and using this information to trigger refresh operations only when necessary. The count data provides feedback about access patterns, allowing the controller to distinguish between normal and malicious access patterns and respond appropriately.
Data Source
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AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit, wherein the first command designates a memory operation on the target memory cell row and is applied after the active command was applied.