Time-Multiplexed Bitcell Architecture for Multi-Port Memory
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Solution Overview
Problem
Conventional bitcells in modern memory applications face inefficiencies due to a large number of transistors requiring many bitlines and wordlines, leading to routing congestion, increased area, and higher power consumption, as well as sensitivity to asymmetric layout and process variations, making them inefficient for multi-port memory applications.
Innovation Solution
A novel bitcell architecture using 9T or 11T configurations with transient Vss/Vdd droop write assist schemes, which reduces the number of transistors and bitlines/wordlines, and implements a double-pumped IO port configuration to increase the number of read-write ports while minimizing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional bitcells use a large number of transistors (18 or more), then more bitlines and wordlines can be supported, but routing congestion within the bitcell increases and area on-chip increases
Solution Approach 1:
The patent merges multiple port functionalities into a reduced transistor bitcell architecture. By using time-multiplexed ports and shared bitlines/wordlines, multiple ports are supported with fewer transistors (6T, 8T, or 10T) than conventional designs, eliminating routing congestion while maintaining multi-port capability
Solution Approach 2:
The bitcell architecture implements universal transistors that can serve multiple functions across different ports. The same transistor network handles read and write operations for multiple ports through time-multiplexing, allowing each transistor to be reused across different port operations rather than dedicating separate transistors to each port
2Adaptability or versatility
If conventional bitcells use a large number of transistors (18 or more), then more bitlines and wordlines can be supported, but area on-chip increases
Solution Approach 1:
The patent combines multiple port operations into a compact bitcell structure with reduced transistor count (6T, 8T, or 10T). By sharing bitlines and wordlines across multiple ports through time-multiplexing, the physical area required is significantly reduced compared to conventional designs that would require separate transistor networks for each port
Solution Approach 2:
The patent transitions from spatial multiplexing (separate physical paths for each port) to temporal multiplexing (time-based sharing of paths). This dimensional change allows multiple ports to share the same physical bitlines and wordlines by assigning different time slots, thereby reducing the area on-chip while maintaining multi-port functionality
3Adaptability or versatility
If conventional bitcells use a large number of transistors (18 or more), then more bitlines and wordlines can be supported, but power consumption increases
Solution Approach 1:
The patent merges multiple port operations into a single compact bitcell network, reducing the total number of active transistors from 18 or more to 6T, 8T, or 10T configurations. This consolidation reduces the overall power consumption while supporting the same number of ports through time-multiplexed access
Solution Approach 2:
The patent implements power gating techniques where transistors are selectively turned off when not in use and recovered when needed. By controlling the timing of transistor activation for different ports and operations, power consumption is reduced while maintaining the capability to support multiple ports on demand
4Adaptability or versatility
If conventional bitcells increase the number of transistors, then more bitlines and wordlines can be supported, but read/write margin decreases due to sensitivity to asymmetric layout and process variation
Solution Approach 1:
The patent optimizes the local characteristics of individual transistors within the bitcell to compensate for process variations and layout asymmetries. By carefully sizing and positioning transistors in the 6T, 8T, or 10T configurations, the design achieves better read/write margins despite the reduced transistor count and increased sensitivity to local variations
Data Source
AI summary
Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.