Bitline Voltage Adjustment for Defective Deck Memory Devices
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Solution Overview
Problem
Memory devices with both defective and functional decks experience increased error rates due to threshold voltage distribution shifts during read operations, as existing read schemes do not account for the unique characteristics of 'half good' memory devices with defective decks.
Innovation Solution
Implementing adaptive adjustment of bitline voltages during the program verify phase, where the memory sub-system controller determines the presence of defective and functional decks and applies a higher PV bitline voltage to compensate for threshold voltage shifts, using data structures to identify and adjust voltages based on deck configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing read schemes are used in memory devices with defective decks, then the device can operate, but error rates increase due to threshold voltage distribution shifts
Solution Approach 1:
The patent implements dynamic adjustment of bitline voltages during the program verify phase based on the detected deck configuration. The system transitions from static read schemes to dynamic voltage adjustment, where the bitline voltage is adaptively changed according to whether defective decks are present, thereby resolving the contradiction between maintaining operational simplicity and adapting to different device states
Solution Approach 2:
The patent changes the bitline voltage parameter during the program verify phase based on the deck configuration. By adjusting the voltage level according to the presence of defective decks, the system compensates for threshold voltage distribution shifts and reduces error rates without requiring a completely new read scheme
2Reliability
If adaptive bitline voltage adjustment is implemented, then error rates are reduced, but device complexity increases
Solution Approach 1:
The patent performs preliminary detection of defective decks during manufacturing or initialization, and stores this information in a data structure. This preliminary action allows the system to retrieve pre-determined voltage adjustment values during operation, avoiding the need for complex real-time analysis and reducing operational complexity
Solution Approach 2:
The patent introduces a data structure as an intermediary between the deck configuration and the voltage adjustment mechanism. This data structure stores the relationship between defective deck patterns and corresponding bitline voltage values, simplifying the control logic by providing a direct lookup mechanism rather than requiring complex computational decisions
3Reliability
If higher PV bitline voltage is applied during program verify, then threshold voltage shifts are compensated, but energy consumption increases
Solution Approach 1:
The patent applies higher bitline voltages only during the program verify phase and only when defective decks are detected, rather than continuously or universally. This localized application of increased voltage compensates for threshold voltage shifts where needed while minimizing unnecessary energy consumption during other operations
Data Source
AI summary
A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.