Bitline Voltage Regulation for Write Disturb Mitigation
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Solution Overview
Problem
High-density non-volatile memory arrays experience severe write disturb effects due to capacitive coupling and bitline leakage, leading to unintended charge alterations in neighboring memory cells during write operations, especially in smaller die size structures.
Innovation Solution
Implementing a bitline driver circuit that actively controls the ramp rate of both the target and neighboring bitlines by applying controlled voltage signals, including a ramped disturb inhibit voltage to neighboring bitlines and an increased source bias voltage during write operations, to minimize potential differences between source and drain nodes of untargeted memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied to the target bitline to change the state of the target memory cell, then write speed is improved, but write disturb effects on neighboring cells worsen
Solution Approach 1:
The patent applies preliminary anti-action by proactively applying a controlled voltage to the neighboring bitline before the write operation begins. This preemptive voltage application counteracts the capacitive coupling effects that would otherwise cause write disturb, allowing the target bitline to reach high voltage quickly for fast writing while the neighboring bitline's voltage is simultaneously controlled to prevent unintended charge injection into neighboring cells
Solution Approach 2:
The patent changes the voltage parameter of the neighboring bitline from a traditional floating state (high impedance) to an actively controlled voltage state. By dynamically adjusting the neighboring bitline voltage to follow the target bitline voltage ramp rate, the system resolves the contradiction between fast writing (requiring rapid voltage changes) and preventing write disturb (requiring controlled voltage differences)
2Productivity
If the ramp rate of the target bitline is increased to enable faster write operations, then write speed is improved, but the potential difference between target and neighboring bitlines increases causing severe write disturb
Solution Approach 1:
The patent changes the voltage parameter of the neighboring bitline from a passive floating state to an actively controlled state that dynamically tracks the target bitline voltage. By controlling the ramp rate of the neighboring bitline to match the target bitline, the system enables fast write operations with high ramp rates while maintaining minimal potential difference between bitlines, thus preventing write disturb and preserving data integrity
3Manufacturing precision
If higher device packing density is achieved by reducing cell size, then manufacturing precision is improved, but capacitive coupling between bitlines increases worsening write disturb
Solution Approach 1:
The patent changes the electrical parameter of the neighboring bitline from a high-impedance floating state to an actively driven voltage state. This parameter change compensates for the increased capacitive coupling inherent in high-density designs by controlling the neighboring bitline voltage to follow the target bitline voltage, thereby enabling high device packing density while mitigating the worsened capacitive coupling effects through active voltage management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces write disturb conditions, enables faster write speeds, and maintains data integrity in neighboring cells by ensuring the neighboring bitline ramp rate closely follows the target bitline, thereby preventing severe write disturbances.
Implementation Method 1
Due to capacitive coupling between metal bitlines, a reverse potential difference can occur between the drain and source nodes of the neighbor cell resulting in an undesired write disturb on the untargeted neighbor cell
Implementation Method 2
some non-volatile memory devices control a ramp rate of the target bitline to enable a more effective 'pull up' of the voltage potential at the floating bitline so that the potential difference between a target cell bitline and the neighboring floating bitline is reduced
Data Source
AI summary
Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a “source” bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.