Read-Only Memories TRIZ Cases

Applying set voltages to unselected memory blocks removes channel holes, enhancing electrical characteristics and program verify performance.

A semiconductor fuse array integrates with memory cell structures to generate control data via electrical states.

Applying four distinct bias levels to the data line reduces programming time and complexity in NAND flash memory.

A wordline ramp rate monitor detects defective memory lines by measuring voltage signal changes during access operations.

Serial NOR memory uses single data rate input and double data rate output to boost read bandwidth.

A control circuit generates an integrated activation signal to simultaneously trigger voltage generation and path connection in nonvolatile memory devices.

A memory device integrates current sensing and fail bit management to optimize read operations.

Raising the array substrate voltage before activating pass gates reduces dielectric stress between conductors, preventing breakdown in erasable memory arrays.

A semiconductor memory programming method applies distinct program pulses to fast and slow cells.

Dynamic voltage selection optimizes EEPROM programming throughput while preserving memory lifetime.

Dynamic read voltage adjustment reduces error decoding failures caused by threshold voltage shifts in non-volatile memory cells.

A read process compensates floating gate coupling by determining adjacent cell conditions using margined reference voltages.

A selective refresh method targets failing non-volatile memory cells using additional reference parameters to distinguish states.

Lower erase-verify voltage on first-programmed word lines ensures consistent cell erasure across memory blocks.

Fuse driver outputs fuse information through a test global line to an I/O driver pad during test mode.

A memory controller tracks erratic bits failing to program correctly within each flash block to assess health status.

A time-based sensing circuit charges a capacitor and discharges it through a programmable resistive element to determine logic states.

Dynamic potential control during test mode screens defective SRAM cells by simulating over-time deterioration, reducing yield loss from random variance.

A cross-bar router employs programmable transistors with electric field-based threshold voltages to establish signal paths.

Selective data line routing connects shared sense circuitry to multiple non-volatile memory arrays, resolving density-versus-programming contradictions.

A memory reading system adjusts reference levels to match known data patterns.

Dividing memory blocks into smaller erase units reduces peak current requirements and power supply complexity while maintaining erasure productivity.

Sacrificial memory cells monitor threshold voltage shifts to dynamically adjust erase pulse voltage, reducing Gm deterioration and improving endurance.

A shared repair circuit generates a unified signal to replace failed word lines across adjacent memory banks using redundant arrays.

Segmented word line voltage boosting reduces lateral electric fields in the NAND channel, preventing hot electron injection into charge storage regions.

A column scramble pattern shifts operational data units across memory blocks, preventing sense line faults from corrupting redundant copies.

Intermediate voltage ramping reduces program disturb by limiting Gate Induced Drain Leakage currents in unselected flash memory cells.

Varying voltage levels isolate carrier contributions to resolve interface trap non-uniformity during program erase cycles.

Internal power switches decouple OTP memory cells from programming voltage to prevent accidental programming and reduce device complexity.

A memory device programs dummy cells with location-dependent threshold voltages to stabilize channel potentials.

Page buffer circuits utilize parasitic capacitance between metal routing lines to eliminate dedicated capacitors and reduce device area.

A memory programming apparatus reads cell states to generate a re-writing pattern that corrects mismatch cells during OTP data writing.

Transfer gates connect sense amplifiers to bit lines only during specific data latching periods, reducing current consumption during serial access.

Sequential test voltages enable self-regulated read voltage determination, reducing operation time and improving data reliability.

Separate switching paths isolate programming currents from sensing comparators, preventing state alteration during accurate fuse detection.

Dynamic select line voltage control reduces program disturb phenomena in semiconductor memory devices, improving multi-state programming reliability.

Vertical stacking with monocrystalline channels suppresses resistance increase while improving integration density and performance.

A nonvolatile memory cell programming method uses periodic charge injection with wait times to stabilize threshold voltage states.

A semiconductor controller couples volatile memory global I/O lines to a dummy pad for non-volatile storage.

A controller adjusts the read enable signal duty cycle to maintain synchronization with data strobe signals.

Grouping NAND flash wordlines with unique temperature coefficients resolves read errors from fixed compensation over- and under-correction.

A memory system generates cumulative distribution function data to identify exceptional units and determine optimal read voltage thresholds.

A second circuit manipulates a flag to abort threshold voltage measurement, reducing read time when upper page data remains unprogrammed.

Active voltage regulation on neighboring bitlines minimizes write disturb effects caused by capacitive coupling in high-density memory arrays.

Segmented global and local decoders control word line selection states to prevent capacitive coupling interference on non-selected lines.

Pre-pulse signals stabilize high-k dielectric polarization, reducing channel current fluctuations and leakage-induced data loss.

A semiconductor calculating part sums bit line currents during read operations to generate multi-bit data.

Data bit inversion logic reduces read error rates by ensuring majority bits program as zeros to minimize incorrect flips.

A common-mode fuse-readout circuit uses differential signals to determine fuse states with high accuracy.