Semiconductor Memory Transfer Gate Control
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Solution Overview
Problem
Conventional FBC memory devices consume high current during serial access due to continuous application of write bias by sense amplifiers, leading to increased power consumption and circuit complexity.
Innovation Solution
The implementation of transfer gates that connect or disconnect sense amplifiers from bit lines only during specific periods of data writing, allowing for reduced current consumption and simplified circuit design by activating the transfer gates after data is latched, thereby minimizing unnecessary power usage and circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sense amplifiers continuously apply write bias to FBCs during serial access, then data writing is maintained, but current consumption increases
Solution Approach 1:
The patent applies periodic action by controlling transfer gates to connect sense amplifiers to bit lines only during specific periods when data writing is required, rather than continuously. The transfer gates are activated selectively during serial access operations to enable current flow only when needed, and deactivated otherwise to reduce power consumption while maintaining data writing capability.
2Use of energy by moving object
If additional circuits are added to connect only selected bit lines to sense amplifiers, then current consumption is reduced, but circuit scale increases
Solution Approach 1:
The patent introduces transfer gates as intermediary switching elements between sense amplifiers and bit lines. These transfer gates act as mediators that selectively connect or disconnect bit lines from sense amplifiers based on access requirements, enabling controlled current flow without requiring complex additional circuitry for line selection.
Solution Approach 2:
The patent applies dynamics by making the connection between sense amplifiers and bit lines dynamic rather than static. The transfer gates can be activated or deactivated based on the access mode (serial or non-serial), allowing the circuit to adapt its configuration to operational requirements without permanent structural changes.
Data Source
AI summary
This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to the gates of the memory cells; bit lines connected to the drains of the plurality of memory cells; sense amplifiers detecting data stored in the memory cells via the bit lines, the sense amplifiers writing data to the memory cells via the bit lines and latching read data or data to be written; and a plurality of transfer gates connecting or disconnecting the sense amplifiers to or from the bit lines, in a period of a serial access for continuously writing the data to the memory cells connected to an activated word line among the word lines, the transfer gates connecting the sense amplifiers to the bit lines corresponding to the sense amplifiers, respectively, after the sense amplifiers corresponding to the memory cells latch the data.