SRAM Cell Stress Testing via Dynamic Potential Control
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Solution Overview
Problem
In advanced semiconductor memory devices, the reduction in transistor size leads to increased random variance in transistor characteristics, making it difficult to maintain good SRAM cell characteristics, especially due to over-time deterioration and operational noise, which results in reduced static noise margin, write level, and cell current, causing defects even in products that pass initial tests.
Innovation Solution
A semiconductor memory device with a control circuit that switches between normal and test modes to control the potential supplied to the source of the load transistor, word line, and bit line, allowing for stress testing and dynamic power supply adjustments to simulate over-time deterioration and operational noise conditions, thereby maintaining appropriate cell characteristic margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor size is reduced to increase integration density, then device area is reduced, but random variance in transistor characteristics increases leading to poor SRAM cell characteristics
Solution Approach 1:
The patent applies preliminary action by performing stress testing during the manufacturing process to identify and screen out memory cells with poor characteristics before they are shipped. This includes applying stress signals to simulate over-time deterioration and operational noise conditions, and screening bits that fail to meet predetermined thresholds for static noise margin, write level, and cell current.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting power supply voltage and applying stress signals during testing to simulate different operational conditions and over-time deterioration effects. This allows the detection of cells that may fail under stressed conditions even if they pass normal operation tests.
2Ease of manufacture
If conventional screening methods are used, then initial product testing is simple, but defective bits are not detected until field operation causing yield loss
Solution Approach 1:
The patent implements preliminary screening during manufacturing by applying stress signals and measuring cell characteristics under stressed conditions. This preliminary action identifies defective bits before shipment, preventing field failures and yield loss while maintaining a relatively simple manufacturing process.
Solution Approach 2:
The patent ensures continuous monitoring and testing of SRAM cell characteristics throughout the manufacturing process and during operation. By continuously assessing cell health through stress testing and dynamic threshold adjustment, the system maintains high reliability without requiring complex intermittent testing procedures.
3Reliability
If stress testing is applied to screen defective bits, then reliability is improved, but testing time and complexity increase
Solution Approach 1:
The patent performs stress testing as a preliminary step during manufacturing before final product completion. By screening out defective bits early in the process using automated stress signal application and measurement, the system improves reliability without significantly extending overall production time.
Solution Approach 2:
The patent implements self-service through built-in self-test (BIST) circuits that can autonomously generate stress signals, measure cell characteristics, and identify defective bits without external testing equipment. This self-testing capability reduces inspection time and complexity while maintaining high screening effectiveness.
4Reliability
If power supply potential is dynamically controlled to maintain cell characteristics, then SRAM performance is improved, but circuit complexity increases
Solution Approach 1:
The patent dynamically controls power supply potential to memory cells during stress testing to simulate different operational conditions and maintain adequate cell characteristic margins. The control circuit adjusts voltage levels based on detected cell states and stress conditions, improving reliability while using standardized control circuitry.
Solution Approach 2:
The control circuit is designed to perform multiple functions: normal read/write operations, stress signal generation, cell characteristic measurement, and dynamic power supply adjustment. This multi-functionality reduces overall system complexity by consolidating control functions into a single integrated circuit rather than requiring separate dedicated circuits for each function.
Data Source
AI summary
A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.