NOR Memory Vertical Stacking Monocrystalline Channel Resistance
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Solution Overview
Problem
Existing NOR-type memory devices face challenges in scaling down due to planar device limitations and vertical device stacking, which leads to increased resistance and reduced performance, while attempting to enhance integration density and performance.
Innovation Solution
A NOR-type memory device is designed with a stack of single crystal material layers, eliminating the need for additional isolation layers between bit lines, and incorporating a gate stack with a memory functional layer, allowing for improved integration density and performance by using a vertical device structure with a select transistor for reduced interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical devices are stacked to increase integration density, then integration density is improved, but resistance increases and performance deteriorates
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to monocrystalline silicon for the channel layer, which fundamentally alters the electrical resistance characteristic. This material parameter change enables maintaining low resistance while achieving vertical stacking and high integration density, directly resolving the contradiction between increased integration density and deteriorated performance
Solution Approach 2:
The patent transitions from planar device arrangement to vertical device stacking, utilizing the vertical dimension to increase integration density. By arranging source, gate, and drain in a direction substantially perpendicular to the substrate surface, the patent achieves higher integration density while managing resistance through monocrystalline material selection
2Ease of manufacture
If polycrystalline silicon is used as channel material for vertical device stacking, then device stacking is facilitated, but resistance increases
Solution Approach 1:
The patent changes the crystalline structure parameter of the channel material from polycrystalline to monocrystalline silicon. This parameter change fundamentally improves the resistance characteristic while maintaining compatibility with vertical device stacking processes, thereby resolving the contradiction between ease of stacking and resistance performance
3Ease of manufacture
If planar device structure is used, then manufacturing is simpler, but scaling down becomes difficult
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking, utilizing the vertical dimension to continue device scaling. By arranging components in a direction perpendicular to the substrate surface, the patent achieves further size reduction while maintaining manufacturing feasibility through established semiconductor fabrication processes
Data Source
AI summary
Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: at least one memory cell layer including a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are stacked on each other; at least one gate stack that extends vertically and includes a gate conductor layer and a memory functional layer between the gate conductor layer and the at least one memory cell layer. A memory cell is defined at an intersection of the gate stack and the memory cell layer. At least one bit line is electrically connected to the second source/drain layer in the memory cell layer; and at least one source line is electrically connected to the first and third source/drain layers in the memory cell layer.