Controller Duty Cycle Correction for NAND Flash Read Enable Signals
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Solution Overview
Problem
The increasing speed of NAND flash memory interfaces leads to a high compression ratio of the data strobe signal, causing duty variation issues in the read enable signal, which affects the valid window and can result in incorrect data latching by the controller due to mismatched duty cycles between the data strobe and read enable signals.
Innovation Solution
A controller with a phase comparator and Duty control unit that compares the phases of the data strobe and delayed data strobe signals to correct the duty cycle of the read enable signal, ensuring it remains at 50%, thereby maintaining proper synchronization and data latching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the interface speed of NAND flash memory is increased, then the data transmission rate is improved, but the duty cycle variation of the read enable signal increases causing invalid window compression
Solution Approach 1:
The patent implements a feedback mechanism where the phase comparator continuously monitors the phase difference between the data strobe signal and delayed data strobe signal, and the duty control unit adjusts the read enable signal duty cycle based on this feedback to maintain the valid window within the required range despite high-speed interface variations
Solution Approach 2:
The patent dynamically changes the duty cycle parameter of the read enable signal based on the phase comparison results, adjusting this parameter in real-time to compensate for interface speed variations and maintain proper timing margins
2Productivity
If the compression ratio of data strobe signal increases due to duty variation, then the interface operates at higher speed, but the valid window becomes too small affecting setup and hold times
Solution Approach 1:
The phase comparator provides continuous feedback on the valid window compression status, enabling the duty control unit to adjust the read enable signal duty cycle to prevent the valid window from becoming too small, thus maintaining reliable data latching at high speeds
Solution Approach 2:
The duty control unit proactively adjusts the read enable signal duty cycle before data latching operations to ensure the valid window maintains sufficient margin for setup and hold times, preventing timing violations before they occur
3Speed
If the duty cycle of read enable signal deviates from 50%, then the interface speed can be increased, but the phase mismatch between data strobe and read enable signal causes incorrect data latching
Solution Approach 1:
The phase comparator continuously monitors phase alignment between data strobe and delayed data strobe signals, providing feedback to the duty control unit which adjusts the read enable signal duty cycle to maintain proper phase alignment even at high interface speeds
Solution Approach 2:
The patent intentionally introduces asymmetry in the control approach by using a phase comparator to detect phase differences and a duty control unit to asymmetrically adjust the read enable signal duty cycle, rather than using symmetric timing adjustments
Data Source
AI summary
According to one embodiment, CONTROLLER includes a phase comparator that receives a data strobe signal outputted from a memory in response to a read enable signal, and a delayed data strobe signal formed by applying a delay to the data strobe signal, and outputs a result of comparison between phases of two signals. The controller also includes a Duty control unit that corrects a Duty of the read enable signal outputted to the memory based upon the comparison result of the phase comparator.