Semiconductor Fuse Array Integration for Density
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Solution Overview
Problem
Existing semiconductor devices face limitations in integration density due to the inability to program general fuses after encapsulation, which is addressed by using e-fuses realized with transistors, but these require larger transistors and amplifiers, restricting further integration density improvements.
Innovation Solution
A semiconductor device incorporating a control signal generator and a fuse array portion that enables a power control signal during the boot-up period, allowing the fuse array to generate data based on electrical open/short states of fuses selected by address signal combinations, thereby enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If e-fuses are used to enable programming after encapsulation, then programmability is improved, but transistor size must be increased which reduces integration density
Solution Approach 1:
The invention divides the fuse array into multiple banks (first fuse bank, second fuse bank, third fuse bank) that can be independently controlled. Each bank can be selectively programmed based on operational mode, allowing the system to achieve adaptability without requiring all fuses to be simultaneously active, thereby improving integration density while maintaining programmability.
Solution Approach 2:
The invention implements dynamic control of fuse banks through mode selection signals that enable or disable specific banks based on operational requirements. The first fuse bank is enabled during normal operation while the second and third fuse banks are disabled, and vice versa during test operations. This dynamic switching allows the system to adapt its functionality without fixed hardware constraints, resolving the contradiction between adaptability and integration density.
2Measurement precision
If amplifiers are used to recognize data in e-fuses, then data recognition accuracy is improved, but device complexity increases which reduces integration density
Solution Approach 1:
The invention merges the fuse array with the memory cell array structure, where fuses are integrated within the existing memory cell architecture rather than being separate components. This integration allows data recognition to occur through the existing memory readout circuits and amplifiers already present in the memory device, eliminating the need for separate amplifier circuits dedicated solely to fuse reading, thereby maintaining measurement precision while reducing device complexity.
Solution Approach 2:
The invention makes the memory device's existing readout circuits and amplifiers serve dual purposes: reading normal memory cell data and reading fuse data. The same column select lines, bit lines, and sense amplifiers used for memory operations are also utilized for fuse array operations, allowing a single set of circuits to perform multiple functions and thereby reducing overall device complexity while maintaining data recognition accuracy.
3Ease of manufacture
If general fuses are used for storing control information, then manufacturing simplicity is improved, but inability to program after encapsulation reduces adaptability
Solution Approach 1:
The invention prepares the fuse array structure in advance during the manufacturing process, integrating the fuses into the memory cell array before encapsulation. The fuse banks are pre-configured with selection circuits and control logic that enable post-encapsulation programming through electrical control. This preliminary preparation maintains manufacturing simplicity while enabling adaptability, as the structure is ready for programming but the actual programming occurs later through electrical means rather than requiring physical access during manufacturing.
Data Source
AI summary
Semiconductor devices are provided. The semiconductor device may include a control signal generator and a fuse array portion. The control signal generator may generate a power control signal, disable the power control signal to a ground voltage signal level during a power-up period, and enable the power control signal to a power supply voltage signal level from a moment that the power-up period terminates until a moment that a mode register set operation terminates. The fuse array portion may execute a boot-up operation while the power control signal is enabled. The fuse array portion may generate fuse data according to an electrical open/short state of a fuse. The fuse may be selected by a level combination of address signals during the boot-up operation.