Non-volatile Memory Row Decoder Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile semiconductor memory devices, such as NOR-type flash memories, face challenges with downsizing due to the large size of row decoders, which causes interference and results in failed read operations due to capacitive coupling between non-selected word lines.
Innovation Solution
A non-volatile semiconductor memory device is designed with a local row decoder and a global row decoder, utilizing MOS transistors to independently select global word lines, allowing for reduced decoder size while preventing capacitive coupling issues, thereby avoiding failed read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the row decoder is configured to prevent capacitive coupling interference, then read reliability is improved, but the number of elements and wires increases, causing interference with downsizing
Solution Approach 1:
The row decoder is divided into a global row decoder and a local row decoder. The global row decoder selects between global word lines GWL1 and GWL2, while the local row decoder selects between local word lines WL1 and WL2. This segmentation allows independent control of different word line groups, preventing capacitive coupling interference while minimizing the number of control elements needed.
Solution Approach 2:
The patent introduces a two-dimensional decoder structure with global and local dimensions. The global row decoder operates at the global word line level, while the local row decoder operates at the local word line level. This dimensional separation enables precise control of individual word lines without requiring additional interference prevention elements.
2Area of moving object
If the row decoder size is reduced for downsizing, then device integration is improved, but capacitive coupling between non-selected word lines causes potential elevation and failed read
Solution Approach 1:
By segmenting the word lines into global word lines (GWL1, GWL2) and local word lines (WL1, WL2) with separate decoders, the patent reduces the row decoder size while maintaining reliable read operations. Each decoder independently controls its designated word lines, preventing capacitive coupling issues without requiring additional interference prevention elements.
Solution Approach 2:
The patent implements dynamic selection of word lines through the global and local row decoders. The global row decoder dynamically selects which global word line to activate, and the local row decoder dynamically selects which local word line to activate. This dynamic control ensures that only the intended word line is active at any given time, preventing capacitive coupling interference while minimizing decoder size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables downsizing of the row decoder while maintaining reliable read operations by independently controlling odd and even global word lines, preventing potential elevation on non-selected word lines and ensuring accurate data retrieval.
Implementation Method 1
capacitive coupling thereof with other word lines elevates the potential on the non-selected word line
Data Source
AI summary
The local row decoder includes a first MOS transistor of a first conductivity type having one end connected to the local word line, the other end supplied with a first voltage, and a gate connected to the global word line, and a second MOS transistor of a second conductivity type having one end connected to the local word line, the other end supplied with a second voltage, and a gate connected to the global word line. The global row decoder is capable of independently selecting either a first global word line or a second global word line. The first global word line is connected to the first MOS transistor and the second MOS transistor both connected to any one of the local word lines. The second global word line is connected to the first MOS transistor and the second MOS transistor both connected to another adjacent local word line.