Semiconductor Memory Read Voltage Self-Regulation via Sequential Test Voltages
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving read operation speed and regulating read voltage efficiently, leading to reduced data reliability due to widened threshold voltage distributions and the need for external controller intervention.
Innovation Solution
The semiconductor memory device incorporates a peripheral circuit that applies sequentially increasing test voltages to the word line, determining the read voltage by comparing data bits between page data sets, allowing the device to regulate its own read voltage and reduce the time required for voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequentially increasing test voltages are applied to regulate read voltage, then voltage regulation capability is improved, but read operation time is increased
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines before applying test voltages to the word line. This preparation step ensures that when test voltages are applied sequentially to determine the optimal read voltage, the bit lines are already in the correct state for rapid data sensing, thereby reducing the overall time penalty of voltage regulation
Solution Approach 2:
The patent implements self-service by enabling the memory device to automatically regulate its own read voltage through internal comparison of data bits read at different test voltages. This self-regulation eliminates the need for external controller intervention, allowing voltage adjustment to occur rapidly within the device itself without adding external regulation overhead time
2Measurement precision
If multiple test voltages are applied to determine optimal read voltage, then read voltage accuracy is improved, but read operation speed is reduced
Solution Approach 1:
The patent applies partial action by using a limited sequence of test voltages (first through kth test voltages) rather than exhaustively testing all possible voltage values. The peripheral circuit compares data bits read at these partial test points to determine the optimal read voltage, achieving sufficient accuracy without the time cost of complete voltage sweeping
Solution Approach 2:
The patent implements periodic action by applying test voltages in a structured sequence with regular timing intervals. The peripheral circuit systematically applies each test voltage, senses the resulting data, and uses this periodic sampling to interpolate or determine the optimal read voltage, converting a potentially continuous time-consuming process into discrete periodic measurements that can be completed faster
Data Source
AI summary
A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.