Selective Refresh for Single Bit Memory Cell Error Reduction
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Solution Overview
Problem
Single bit per cell (SBC) mode in memory devices experiences increased data failure rates as memory cell sizes decrease, leading to heightened read errors due to charge coupling between cells, and existing error reduction techniques compromise user functionality or increase memory device size and wear.
Innovation Solution
A selective refresh method for non-volatile memory cells using additional reference parameters to distinguish refresh states, allowing for targeted correction of failing cells without global refresh, thereby reducing ECC overhead and user programming restrictions, and integrating with wear leveling to optimize memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are decreased to increase bit density, then storage capacity is improved, but data failure rates and read errors increase due to charge coupling between cells
Solution Approach 1:
The patent segments the memory array into multiple blocks and implements refresh operations at the block level rather than cell level. This segmentation allows targeted refresh of affected blocks while leaving other blocks operational, thereby maintaining high bit density while reducing read errors through selective refresh of charge-coupled cells
Solution Approach 2:
The patent performs preliminary detection of charge coupling conditions by monitoring threshold voltage distributions and identifying blocks prone to charge coupling errors before they cause data failures. This preliminary action enables proactive refresh operations that prevent read errors while maintaining high bit density in scaled memory cells
2Reliability
If global refresh is implemented to reduce read errors, then reliability is improved, but memory device size and wear increase
Solution Approach 1:
The patent implements local quality by applying refresh operations selectively to specific blocks that exhibit charge coupling characteristics rather than performing global refresh across the entire memory device. This local approach reduces the effective refresh burden and device wear while maintaining reliability in affected areas, avoiding the need to increase overall device size
Solution Approach 2:
The patent changes operational parameters by adjusting refresh timing and thresholds based on detected charge coupling conditions. By dynamically modifying refresh parameters rather than using fixed global refresh schedules, the system reduces unnecessary refresh operations, thereby decreasing device wear and complexity while maintaining read error rates within acceptable limits
3Reliability
If error reduction techniques are applied to SBC mode, then read errors are reduced, but user functionality is compromised due to programming restrictions
Solution Approach 1:
The patent implements self-service by enabling the memory controller to automatically detect charge coupling conditions and perform refresh operations without requiring user awareness or intervention. This self-managing approach reduces read errors through intelligent refresh while maintaining full user functionality, as users experience no programming restrictions or operational differences from standard SBC mode
Data Source
AI summary
Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans its memory cells, performing a multi-level read on memory cells in a single bit per cell mode. Depending on the state sensed, the cell is refreshed to a correct state if necessary. In one embodiment, the memory scan is appended to a user erase operation, a flash block is swapped with another bock if the state sensed indicates charge gain, and a flash cell is programmed up if the state sensed indicates charge loss.