OTP Memory Circuit Power Switch Isolation

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Solution Overview

Problem

One-time programmable (OTP) memory cells are vulnerable to accidental programming during ungraceful power-down events, leading to irreversible data corruption and potential safety issues, especially in devices like medical equipment or vehicles, due to the lack of effective protection mechanisms.

Innovation Solution

Implementing an OTP memory circuit with internal power switches that decouple memory cells from programming voltage during power-down events, using a shared voltage regulator and redundant protection mechanisms to prevent accidental programming, thereby maintaining the memory in a non-program state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate voltage regulator is used for the OTP memory array to isolate it from other device circuits, then the reliability of OTP memory cells is improved, but the device complexity and cost increase

Engineering Contradiction:
ImproveOTP memory cell protectionVSAvoidvoltage regulator configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the OTP memory array with the main device circuits under a shared voltage regulator, eliminating the need for a separate voltage regulator. Internal power switches are used to provide protection while sharing the common voltage regulator, thus reducing device complexity and cost while maintaining reliability through the switch-based isolation mechanism.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces internal power switches as intermediary elements between the OTP memory array and the shared voltage regulator. These switches act as mediators that can isolate the OTP memory cells from programming voltage during power-down events, providing protection without requiring a separate voltage regulator, thus resolving the contradiction between reliability and device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If internal power switches are used to decouple OTP memory cells from programming voltage during power-down events, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
Improveprotection against accidental programmingVSAvoidinternal power switch configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the power supply control into multiple internal power switches that can independently control different portions of the OTP memory array. This segmentation allows selective isolation of memory cells during power-down events, providing targeted protection while managing complexity through modular switch control rather than a single complex isolation mechanism.

Inventive Principle:
Principle #1Segmentation

3Reliability

If OTP memory cells are protected during power-down events, then the reliability is improved, but the manufacturing cost increases

Engineering Contradiction:
Improveprotection mechanismVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the protection function into the existing OTP memory array design by incorporating internal power switches that share the common voltage regulator. This approach eliminates the need for separate protection circuits and additional voltage regulators, thereby reducing manufacturing complexity and cost while maintaining reliable protection against accidental programming during power-down events.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP2847765B1Circuits configured to remain in a non-program state during a power-down event
Publication Date: 2017.03.08 QUALCOMM INC
  • EP2847765B1 patent drawing
  • EP2847765B1 patent drawing
  • EP2847765B1 patent drawing

AI summary

[0071] In a particular embodiment, an apparatus includes a one- time programmable (OTP) memory circuit (324) configured to be responsive to a programming voltage (308). The OTP memory circuit includes an OTP memory array (220) including OTP memory cells, a first power switch (326) configured to decouple the OTP memory array (220) from the programming voltage (308), and a second power switch (328) configured to decouple a subset of the OTP memory cells from the programming voltage (308). Control logic (216) controls the power switches (326, 328) and is configured to maintain the OTP memory array (220) in a non-program state during a power-down event