Non-Volatile Memory Arrays with Selective Sense Circuitry
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Solution Overview
Problem
Current non-volatile memory technologies, such as EEPROM and flash memory, face limitations in memory density, programming flexibility, and random access capabilities, with EEPROM having large cell size and limited density, and flash memory sacrificing byte-level programming for higher density and speed.
Innovation Solution
The implementation of a three-transistor memory cell device with a NAND architecture, which includes sense circuitry and page buffers, allows for byte-level programming, reduced bit line capacitance, and random access without the need for logical-to-physical address tables, by using select gates to control memory cell access and utilizing backup pages for data integrity during transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If EEPROM is used for non-volatile memory, then byte-level programming capability is maintained, but memory density is limited due to larger cell size
Solution Approach 1:
The memory array is divided into multiple blocks, with each block containing multiple pages of memory cells. This segmentation allows selective programming of individual pages (byte-level granularity) while maintaining high density through efficient block organization and shared sense circuitry across multiple blocks.
Solution Approach 2:
The sense circuitry is designed to serve multiple blocks simultaneously, allowing a single sense amplifier to read from or program multiple memory blocks. This multi-functionality reduces the total number of sense circuits needed, increasing memory density while preserving byte-level programming capability through page-select lines.
2Quantity of substance
If NOR architecture flash memory is used, then memory cell size is reduced for greater density, but byte-level programming is lost and erase operation becomes block-based
Solution Approach 1:
The memory is organized into blocks containing multiple pages, where each page can be independently programmed. This page-based segmentation enables byte-level programming within a page while maintaining the high density of NOR flash architecture through efficient block structure and shared read paths.
Solution Approach 2:
Page buffers are introduced as intermediary structures between the sense circuitry and the memory cells. These buffers temporarily hold data during programming operations, enabling precise byte-level control and programming of individual pages while the underlying NOR architecture maintains high density through block organization.
3Quantity of substance
If NAND architecture flash memory is used, then memory cell density is increased and programming speed is improved, but random reading capability is eliminated and only page-based reading is possible
Solution Approach 1:
The memory array is segmented into multiple blocks, each containing multiple pages that can be independently accessed. This block-page structure enables random reading of specific pages by selecting the appropriate block and page, while maintaining the high density and fast programming characteristics of NAND architecture through series-connected cell strings within each block.
Data Source
AI summary
Memories include first and second arrays of non-volatile memory cells, a first plurality of data lines containing a first number of data lines selectively connected to respective subsets of the first array of non-volatile memory cells, a second plurality of data lines containing a second number of data lines, less than the first number, selectively connected to respective subsets of the second array of non-volatile memory cells, and sense circuitry selectively connected to the first and second pluralities of data lines. The memories are configured, when reading the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines, and the memories are configured, when reading the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.