SPI NOR Memory SDR Input DDR Read Optimization
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Solution Overview
Problem
Conventional SPI NOR flash memory devices face inefficiencies in program operations due to the majority of program time being spent on cell array write time, which is not significantly improved by increasing operating frequency, while read operations benefit from higher data output bandwidth but not program operations.
Innovation Solution
Implementing a serial NOR memory device that uses Single Data Rate (SDR) mode for receiving serial input data and Double Data Rate (DDR) mode for transmitting serial output data, optimizing read performance while maintaining write performance by using SDR mode for data input and DDR mode for data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating frequency is increased to increase data output bandwidth, then read performance is improved, but program operation time is not significantly improved
Solution Approach 1:
The patent segments the data transfer operations into two distinct modes: SDR (Single Data Rate) mode for write operations and DDR (Double Data Rate) mode for read operations. This segmentation allows each operation type to use the most appropriate transfer mode, optimizing both read and write performance independently rather than using a single frequency for both operations.
Solution Approach 2:
The patent implements dynamic mode switching between SDR and DDR based on the operation type. The memory device dynamically selects SDR mode for write operations to maintain compatibility and stable input signaling, while switching to DDR mode for read operations to maximize data output bandwidth. This dynamic adaptation resolves the contradiction by allowing high frequency operation for reads without compromising write operation stability.
2Productivity
If operating frequency is increased, then data output bandwidth is improved, but input signal reliability deteriorates
Solution Approach 1:
The patent applies different quality characteristics to different data transfer directions: SDR mode with wider input windows and more relaxed timing requirements for input operations, and DDR mode with higher bandwidth for output operations. This local differentiation of signal quality requirements allows high-speed output while maintaining reliable input signaling.
Solution Approach 2:
The memory device dynamically adjusts its input/output mode based on operation type. During write operations, it uses SDR mode which provides wider input windows and more tolerant timing, ensuring reliable input signal capture. During read operations, it switches to DDR mode which doubles the data output bandwidth. This dynamic adjustment resolves the contradiction between input reliability and output bandwidth.
3Reliability
If SDR mode is used for data input, then input window width is increased for reliable data fetching, but data output bandwidth is reduced
Solution Approach 1:
The patent segments the data transfer functionality into independent SDR and DDR modes that can be selectively applied to input and output operations. Write operations use SDR mode for reliable input with wide input windows, while read operations use DDR mode for high bandwidth output. This segmentation allows each direction to be optimized independently without compromise.
Solution Approach 2:
The memory device implements multi-functionality by supporting both SDR and DDR modes within the same device architecture. The device can universally handle both input and output operations using either mode depending on the operation type, providing flexibility to optimize input reliability with SDR while achieving high output bandwidth with DDR.
Data Source
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AI summary
A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output data using the double data rate mode.