Flash Memory Calculating Part for AI Matrix Operations
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Solution Overview
Problem
Conventional synapse array devices with flash memory lack a data calculation function, resulting in low data transmission efficiency and time-consuming AI learning processing due to the inability to perform matrix operations.
Innovation Solution
A semiconductor device with a NOR type or NAND type memory cell array that calculates the sum of currents flowing in bit lines during reading operations, enabling matrix operations and improving processing efficiency for AI learning by incorporating a calculating part that performs analog/digital conversion to generate multi-bit data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory is used for storing learning data without calculation function, then storage capability is provided, but data transmission efficiency deteriorates and processing time increases
Solution Approach 1:
The patent combines the flash memory array with calculation functionality by utilizing the current flow through memory cells during read operations to perform matrix operations. The memory array is configured to not only store data but also to execute calculations by leveraging the electrical characteristics of the memory cells themselves, merging storage and computation into a single integrated structure.
Solution Approach 2:
The flash memory array is designed to serve multiple functions: data storage, data reading, and calculation execution. By configuring the memory cells to participate in both storage and computational operations, the system eliminates the need for separate calculation units, allowing the same hardware infrastructure to handle both data retention and processing tasks.
2Device complexity
If conventional flash memory without calculation function is used, then device simplicity is maintained, but AI learning processing time increases
Solution Approach 1:
The memory array performs self-calculation by utilizing its own structural characteristics and current flow properties to execute matrix operations during read operations. The memory cells themselves participate in the calculation process without requiring external calculation hardware, allowing the storage device to serve its own computational needs.
Solution Approach 2:
The patent exploits changes in electrical parameters (current flow, voltage) during memory read operations to encode calculation results. By interpreting the current flow characteristics of the memory cells during reading, the system extracts computational outputs from the same physical process used for data retrieval, eliminating the need for separate calculation steps.
3Measurement precision
If matrix operations are performed externally, then calculation accuracy can be maintained, but data transmission requirements increase and efficiency decreases
Solution Approach 1:
The calculation process is segmented into operations that can be performed locally within the memory array structure itself, rather than requiring all calculations to be offloaded to external processors. The memory array handles computational tasks internally using its inherent electrical characteristics, reducing the volume of data that needs to be transmitted externally while maintaining calculation accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the calculating ability and processing efficiency of AI learning by allowing matrix operations within the semiconductor device, effectively addressing the limitations of existing synapse array devices.
Implementation Method 1
calculating the sum of the currents flowing in the column direction of the bit lines when each row is read
Implementation Method 2
performing analog/digital conversion (A/D) on the sum of the currents in the column direction or the sum of the currents in the matrix direction to generate multi-bit data
Data Source
AI summary
A semiconductor device is capable of improving calculating ability and processing efficiency in AI learning and the like. A flash memory (100) includes a NAND-type or NOR-type memory cell array (110) and a calculation processing part (190). The calculation processing part (190) includes a bit line current detection part (200); a voltage holding part (210) holding a voltage corresponding to the detected current; an adding part (220) adding voltages held by the voltage holding part (210); and an A/D conversion part (230) performing A/D conversion on an addition result of the adding part (220). The calculation processing part (190) may calculate a sum of the current flowing in a bit line in a row direction and/or a column direction when the memory cell array is read.