Parasitic Capacitor Page Buffer Memory Devices
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Solution Overview
Problem
Integrated circuit memory devices face challenges in reducing the size of memory devices due to the large area required by actual sensing capacitors in page buffer circuits, which limits the miniaturization of memory devices.
Innovation Solution
The use of parasitic capacitors formed between existing metal routing lines in page buffer circuits, such as the global data bus (DBUS) metal lines, eliminates the need for actual capacitors and extra metal routing, allowing for larger sensing capacitance without increasing the device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If actual sensing capacitors are used in page buffer circuits, then sensing capacitance is provided, but device area increases
Solution Approach 1:
The patent converts the harmful parasitic capacitance formed by existing metal routing lines into a beneficial sensing capacitor. Instead of adding separate sensing capacitors that would increase area, the invention utilizes the naturally occurring parasitic capacitance between adjacent metal lines (such as DBUS and IDL lines) as the sensing capacitor, thereby eliminating the area penalty while maintaining sensing functionality
Solution Approach 2:
The existing metal routing infrastructure serves dual purposes: it provides data bus functionality and simultaneously creates parasitic capacitance that functions as the sensing capacitor. The metal lines serve themselves by generating the required capacitive effect through their geometric arrangement and proximity, eliminating the need for dedicated capacitor structures
2Reliability
If actual sensing capacitors are used in page buffer circuits, then sensing function is enabled, but device complexity increases
Solution Approach 1:
The existing metal routing lines perform multiple functions simultaneously: they serve as data bus conductors for signal transmission and as sensing capacitors for data detection. This multi-functionality eliminates the need for separate dedicated capacitor structures and reduces overall circuit complexity while maintaining complete sensing functionality
3Area of stationary object
If parasitic capacitors are used instead of actual capacitors, then device area is reduced, but capacitor variation increases
Solution Approach 1:
The patent controls and optimizes the geometric parameters of the metal routing lines (width, spacing, length, and arrangement) to achieve stable and consistent parasitic capacitance values. By carefully designing these physical parameters, the variation in parasitic capacitance is minimized, providing reliable sensing performance across different process conditions and devices
4Area of stationary object
If parasitic capacitors are used instead of actual capacitors, then device area is reduced, but power consumption increases
Solution Approach 1:
The parasitic capacitance is formed naturally by the existing metal routing infrastructure without requiring additional power-consuming capacitor structures or active compensation circuits. The geometric arrangement of metal lines self-generates the required capacitive effect, eliminating the need for external power management associated with traditional capacitor implementations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller device sizes, reduces capacitor variation, minimizes power consumption, and improves sensing accuracy by utilizing existing metal lines to form parasitic capacitors, thereby enhancing overall device performance.
Implementation Method 1
Each DBUS section can be configured to form a parasitic capacitor with at least one inner conductive line in the page buffer for the data sensing
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Systems, methods, circuits, and apparatus for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, a page buffer circuit including a plurality of page buffers, and a cache data latch (CDL) circuit including a plurality of caches coupled to the plurality of page buffers through a plurality of data bus sections. The plurality of data bus sections are configured to be conductively connected together as a data bus for data transfer. Each data bus section corresponds to a page buffer in the page buffer circuit and is configured to conductively separate from at least one adjacent data bus section for data sensing in the memory cell array.