Semiconductor Memory Programming Method for Threshold Voltage Distribution
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Solution Overview
Problem
Semiconductor memory devices face challenges with increased integration, including coupling between neighboring cells and wider threshold voltage distribution, which result in longer programming times.
Innovation Solution
A programming method that applies different program pulses to memory cell groups, determining fast and slow cells, and adjusting voltages to optimize programming speed by using an incremental step pulse programming (ISPP) method, where verify voltages are applied to differentiate and accelerate the programming of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of the semiconductor memory device is increased, then the storage capacity is improved, but the coupling between neighboring cells occurs and the threshold voltage distribution width increases
Solution Approach 1:
The patent divides the memory cell array into multiple groups (first memory cell group, second memory cell group) and applies different program pulses to each group. This segmentation allows independent control of programming operations for different cell groups, enabling precise management of threshold voltage distribution across the integrated array while maintaining high storage capacity.
Solution Approach 2:
The patent applies different program pulse characteristics (first program pulse, second program pulse) to different memory cell groups based on their specific programming needs. Fast cells receive one type of program pulse while slow cells receive another, allowing localized optimization of programming parameters for each cell group to maintain narrow threshold voltage distribution despite high integration.
2Quantity of substance
If the degree of integration is increased to improve storage capacity, then more memory cells are packed, but programming time increases due to wider threshold voltage distribution
Solution Approach 1:
The patent dynamically adjusts programming parameters by classifying cells into fast and slow groups and applying different program pulses accordingly. This dynamic adaptation allows the programming operation to optimize for each cell's characteristics, significantly reducing overall programming time while maintaining narrow threshold voltage distribution in highly integrated devices.
Solution Approach 2:
The patent changes programming parameters (program pulse voltage, pulse width) based on cell classification. By modifying programming parameters according to whether cells are fast or slow, the system achieves efficient programming across all cells in parallel, reducing total programming time despite increased integration density.
3Device complexity
If conventional programming is used to program all cells, then the process is simple, but programming time increases due to waiting for slow cells
Solution Approach 1:
The patent segments the programming process into parallel operations for fast cells and slow cells. By dividing cells into groups and applying appropriate program pulses simultaneously to each group, the system eliminates the need to wait for slow cells to complete programming, thereby reducing total programming time while maintaining manageable process complexity.
Solution Approach 2:
The patent enables continuous programming operations by classifying cells and applying suitable program pulses to different groups simultaneously. This allows the programming process to continue without interruption or waiting periods, as fast cells and slow cells are programmed in parallel with optimized parameters, maximizing productivity.
Data Source
AI summary
A programming method of a semiconductor memory device includes, in an n-th program loop, applying a first program pulse to a first memory cell group, applying a second program pulse to a second memory cell group, and determining first fast cells and first slow cells in the first memory cell group, and in an n+1-th program loop, applying a third program pulse, which is increased by a step voltage from the first program pulse, to the first fast cells in the first memory cell group, and applying a fourth program pulse, which is increased by the step voltage from the second program pulse, to the first slow cells in the first memory cell group and the second memory cell group.