NAND Memory Erase-Verify Voltage Control for Uniform Depth
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Solution Overview
Problem
In semiconductor memory devices, the erase operation often results in incomplete erasure due to insufficient lowering of threshold voltage (Vth) in memory cells, leading to increased error rates and potential uncorrectable errors, especially when some word lines are programmed while others are erased, causing the Vth of erased cells to overlap with programmed states.
Innovation Solution
An erase technique is implemented where the erase-verify voltage for a first-programmed word line is set lower than for remaining word lines, ensuring a uniform erase depth regardless of the number of programmed word lines, and this voltage can be adjusted based on program-erase cycles to optimize erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform erase-verify voltage is applied to all word lines, then the erase operation is simple to implement, but the erase depth becomes non-uniform when some word lines are programmed and others are erased, causing threshold voltage overlap between erased and programmed states
Solution Approach 1:
The patent applies different erase-verify voltages to different word lines based on their programming state. Specifically, a first erase-verify voltage is applied to the first-programmed word line while a second erase-verify voltage is applied to remaining word lines. This local differentiation ensures that each word line receives the appropriate voltage for its state, achieving uniform erase depth across all word lines while avoiding threshold voltage overlap between erased and programmed states.
2Reliability
If the erase-verify voltage is increased to ensure complete erasure of all word lines, then erasure completeness improves, but the first-programmed word line may be over-erased causing threshold voltage to drop below the erased state level
Solution Approach 1:
The patent implements local quality by assigning different erase-verify voltages to different word lines. The first-programmed word line receives a lower first erase-verify voltage that prevents over-erasure and maintains threshold voltage within the erased state range, while remaining word lines receive a higher second erase-verify voltage that ensures complete erasure. This resolves the contradiction by tailoring the voltage level to the specific needs of each word line's programming state.
Solution Approach 2:
The patent identifies and marks the first-programmed word line before the erase operation begins. This preliminary identification allows the erase operation to apply the appropriate lower erase-verify voltage to this specific word line, preventing over-erasure while ensuring other word lines receive sufficient erasure voltage. The preliminary action of identifying the first-programmed word line enables precise voltage control during the subsequent erase operation.
3Productivity
If the erase operation uses a single verify voltage for all word lines, then the operation time is reduced, but the error rate increases due to incomplete erasure of some word lines
Solution Approach 1:
The patent applies local quality by using different erase-verify voltages for different word lines simultaneously during the erase operation. This allows the erase operation to proceed efficiently without sequential verification, maintaining high productivity while ensuring each word line is erased to the appropriate depth. The first-programmed word line uses a lower voltage to prevent over-erasure, while remaining word lines use a higher voltage to ensure complete erasure, thereby reducing error rates.
Data Source
AI summary
An erase operation for a memory cells in a block provides a consistent and sufficient erase depth regardless of the number of programmed word lines in the block. A lower erase-verify voltage is used for a first-programmed word line of a set of word lines than for remaining word lines in the set. As a result, the resistance of a memory cell of the first-programmed word line dominates during sensing of the NAND string so that the number of erase loops can be controlled in a predictable way regardless of the number of programmed word lines. The lower erase-verify voltage can be optimized so that it does not change the number of erase loops to complete an erase operation, compared to the case where a common erase-verify voltage is used on all word lines.