Erase Sequencing for Memory Array Dielectric Stress Reduction
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Solution Overview
Problem
The challenge in solid-state memory architecture is the increased dielectric stress during erase operations, which can lead to dielectric breakdown due to high electric fields between closely spaced conductors, particularly during erase operations where the voltage difference is significant, exceeding the silicon dioxide breakdown voltage.
Innovation Solution
A revised control sequence for select-gate array lines during erase operations, where global select-gates are grounded initially and only driven to the desired voltage after the array substrate voltage reaches a preselected initiation voltage, reducing the voltage difference and stress on local select-gates to levels comparable to programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global SGS/SGD conductors are biased to Vpass voltage during erase operation, then wordlines can be fully discharged, but dielectric stress between conductors increases to dangerous levels
Solution Approach 1:
The patent applies preliminary action by raising the array substrate voltage (Iso-Pwell) to a high voltage (e.g., 20V) before initiating the erase operation. This pre-conditioning of the substrate voltage ensures that when the pass gate is activated and wordlines are discharged, the resulting voltage differences are absorbed by the elevated substrate potential, thereby preventing excessive dielectric stress between conductors while maintaining effective erase functionality.
2Productivity
If feature size is reduced to increase memory capacity, then circuit real estate utilization improves, but electric field strength increases causing dielectric breakdown
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the array substrate voltage (Iso-Pwell) based on the erase operation requirements. By raising the substrate voltage to a high level (e.g., 20V) before erase and maintaining it during the operation, the patent changes the voltage reference level, which effectively reduces the voltage differential across conductor gaps. This parameter adjustment allows continued operation with reduced feature sizes without causing dielectric breakdown, as the electric field strength is controlled through the elevated substrate potential.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dielectric stress and the likelihood of breakdown, enhancing the reliability and operational lifetime of memory devices by maintaining stress conditions similar to those during programming operations.
Implementation Method 1
voltages impressed on conductors located close together can provide a strong electric field that contributes to the breakdown of thin dielectric layers
Implementation Method 2
the dielectric stress in semiconductor memory may be more severe during erase operations than for programming operations
Data Source
AI summary
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.