Flash Memory Erase Pulse Voltage Control
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Solution Overview
Problem
In NAND flash memory, the increasing number of program/erase cycles leads to deterioration of transconductance (Gm), making erasing more difficult and reducing endurance and data retention characteristics, as the erase pulse frequency increases, causing stress on memory cells and potential over-erasing or under-erasing issues.
Innovation Solution
The implementation of sacrificial memory cells programmed with different write levels, which apply a monitor erase pulse to optimize the erase pulse voltage, reducing the number of erase pulses applied and minimizing stress on memory cells by dynamically adjusting the voltage based on verification results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the number of program/erase cycles increases, then the threshold control becomes easier for programming, but the transconductance (Gm) deteriorates and erasing becomes more difficult
Solution Approach 1:
The patent dynamically adjusts the erase pulse voltage based on the number of program/erase cycles performed. As cycle count increases, the erase pulse voltage is increased to compensate for Gm deterioration, transforming a static erase process into a dynamic one that adapts to device degradation.
Solution Approach 2:
The patent changes the erase pulse voltage parameter in response to increasing cycle counts. By modifying this critical parameter, the system maintains effective erasing capability despite the underlying physical degradation of the memory cells' transconductance.
2Productivity
If the erase pulse frequency increases to improve erasing speed, then productivity improves, but stress on memory cells increases and Gm deteriorates
Solution Approach 1:
Instead of increasing erase pulse frequency, the patent changes the voltage parameter of the erase pulse. This alternative parameter adjustment achieves effective erasing without the harmful side effect of increased stress from higher frequency pulsing.
Solution Approach 2:
The patent converts the harmful effect of Gm deterioration into a useful signal. By monitoring threshold voltage changes that result from Gm degradation, the system uses this degradation information to adjust erase pulse voltage, turning the harmful degradation into a feedback mechanism for optimizing erase operations.
3Reliability
If the erase pulse voltage is increased to improve erasing capability, then erasing reliability improves, but the number of erase pulses required increases and stress on memory cells increases
Solution Approach 1:
The patent performs preliminary monitoring of threshold voltage in sacrificial memory cells before applying erase pulses to the entire block. This preliminary action provides advance information about the required erase pulse voltage, allowing the system to set the optimal voltage from the start and avoid iterative adjustments that would increase erasing time.
Solution Approach 2:
The patent implements a feedback mechanism where threshold voltage monitoring results from sacrificial memory cells are used to determine the erase pulse voltage for the entire block. This feedback loop ensures that the correct voltage is applied, achieving reliable erasing in a single pass without requiring multiple iterative pulses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method optimizes erasing without significantly increasing erase pulse frequency, reducing Gm deterioration and improving endurance and data retention characteristics by dynamically adjusting the erase pulse voltage based on the monitoring of sacrificial memory cells.
Implementation Method 1
when data is erased, electrons are released from the floating gate, shifting the threshold voltage of the memory cell in the negative direction
Implementation Method 2
the number of times the erase pulse is applied increases, the number of applying stress on the memory cell increases, the deterioration of the Gm of the memory cell accelerates
Data Source
AI summary
A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.