Four-level data line biasing for NAND flash programming speed
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Solution Overview
Problem
Current memory devices using NAND flash technology face inefficiencies in programming operations due to the need for multiple passes to achieve four data line bias levels, which increases programming time and complexity.
Innovation Solution
Implementing a memory device architecture that utilizes four data line bias levels during programming operations, allowing for reduced programming time by optimizing the biasing of data lines to target threshold voltages more efficiently, thereby reducing the number of program pulses required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple passes are used to achieve four data line bias levels, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent segments the programming operation into four distinct bias levels (first through fourth bias levels) applied sequentially to the data line. Each bias level corresponds to a specific threshold voltage target, allowing precise control of charge transfer in discrete steps. This segmentation enables accurate programming while reducing the total number of passes needed compared to traditional single-level or two-level approaches.
Solution Approach 2:
The patent changes the bias level parameter of the data line dynamically during the programming operation. By transitioning through four different bias levels (e.g., from first bias level to second, third, and fourth bias levels), the system adjusts the electrical conditions to achieve different threshold voltage targets. This parameter change approach allows multiple programming targets to be reached within a single pass, reducing overall programming time while maintaining precision.
2Manufacturing precision
If multiple passes are used to program memory cells, then data state accuracy is improved, but programming complexity increases
Solution Approach 1:
The patent implements a universal programming scheme where a single programming pass can target multiple threshold voltage levels by utilizing four different bias levels. The same programming circuitry and control logic are used regardless of which threshold voltage target is desired, making the system multi-functional. This approach maintains data state accuracy while avoiding the need for separate dedicated circuits or complex multi-pass sequences for different programming targets.
Solution Approach 2:
The patent employs dynamic bias level selection during the programming operation. The bias level applied to the data line is adjusted based on the desired threshold voltage target, allowing the system to adapt to different programming requirements in real-time. This dynamic approach simplifies the overall programming complexity by using a flexible, adaptive method rather than rigid, predetermined multi-pass sequences.
3Productivity
If four data line bias levels are implemented, then programming speed is improved, but control complexity increases
Solution Approach 1:
The patent applies bias levels to the data line in a predetermined sequence (first, second, third, and fourth bias levels) during the programming operation. This preliminary structuring of the bias level application allows the programming circuitry to be optimized for this specific sequence, reducing the real-time control complexity. The control logic is designed to automatically transition through the bias levels in the correct order, enabling high programming speed without proportionally increasing control complexity.
Data Source
AI summary
Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.