Resistive Memory Erase Unit Segmentation for Peak Current Reduction
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Solution Overview
Problem
Conventional methods for erasing resistive memory cells in semiconductor devices require high peak current levels, leading to increased complexity and size of the power supply, as they typically erase all memory cells connected to a memory block simultaneously.
Innovation Solution
The approach divides the memory cell array into smaller erase units with fewer word lines and bit lines than a standard memory block, allowing for simultaneous erasure of memory cells with reduced peak current requirements, and dynamically adjusts the erase unit size based on available power capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all memory cells connected to a memory block are erased simultaneously, then the erasure operation is completed in one step, but high peak current levels are required
Solution Approach 1:
The memory block is divided into multiple erase units, each containing a subset of word lines. Instead of erasing all memory cells in the block simultaneously, the erasure operation is segmented into multiple smaller operations on individual erase units. This reduces the peak current required for each operation while maintaining overall erasure productivity.
2Reliability
If high peak current levels are used for erasure, then complete erasure of memory blocks is achieved, but the power supply complexity and size increase
Solution Approach 1:
By segmenting the memory block into smaller erase units, the power supply only needs to provide high current to a subset of word lines at any given time. This reduces the overall power supply capacity requirements and simplifies the power supply design, while still achieving complete erasure through multiple sequential operations on different erase units.
3Loss of time
If the erase unit size is increased to match the memory block size, then fewer erasure operations are needed, but the peak current requirement increases
Solution Approach 1:
The erase unit size is made dynamic and configurable rather than fixed. The control logic can adjust the number of word lines included in each erase unit based on the available power capacity and operational requirements. This allows optimization between the number of operations and peak current requirements depending on the specific use case.
Data Source
AI summary
A resistive memory device that simultaneously erases memory cells connected to selected word line(s) included in an erase unit. The erase unit includes fewer word lines than are included in a memory block of the resistive memory device. However, erase verification may nonetheless be performed on a block basis.