Memory Device Fail Bit Counting Circuit
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Solution Overview
Problem
Memory devices face challenges in efficiently counting fail bits during read operations, leading to slower speeds and increased circuit sizes due to limitations in current sensing and fail bit management.
Innovation Solution
The implementation of a memory device with a current sensing circuit and a fail bit manager that compares sensed data to a reference voltage, adjusts the allowable number of fail bits, and compensates by changing the fail bit code and compensation values to ensure successful read operations, thereby reducing circuit size and improving read operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional fail bit counting method is used during read operations, then the read operation can be completed, but the circuit size increases and the read speed decreases
Solution Approach 1:
The patent merges the fail bit counting function with the current sensing circuit by using the same sensing nodes and current paths. The page buffer group that normally senses data currents is also used to sense fail bit currents, eliminating the need for separate counting circuitry. This integration directly reduces circuit size while maintaining read operation speed.
Solution Approach 2:
The current sensing circuit is designed to perform multiple functions: it senses both normal data currents during read operations and fail bit currents during verification. The same sensing nodes, current mirrors, and comparison circuits are reused for both purposes, making the circuit universal and reducing overall complexity.
2Reliability
If the allowable number of fail bits is increased to compensate for errors, then read operation reliability improves, but the measurement precision of fail bit detection decreases
Solution Approach 1:
The patent implements a dynamic fail bit management system where the allowable fail bit count is not fixed but adjusted based on read operation results. When read failures occur, the system dynamically increases the allowable fail bit threshold and retries the operation. This dynamic adjustment maintains measurement precision for individual fail bit detection while improving overall read reliability through adaptive compensation.
Solution Approach 2:
The system uses feedback from read operation results to adjust the fail bit management strategy. The fail bit manager monitors read failures and dynamically modifies the allowable fail bit count based on this feedback, enabling the system to adapt to varying memory conditions and maintain both precision and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster read operations and reduces circuit size by effectively managing fail bits and compensating for errors, enhancing the overall performance of memory devices.
Implementation Method 1
a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code
Data Source
AI summary
The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.