Vertical Channel Memory Structure for Density and Yield Balance
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Solution Overview
Problem
As design rules for semiconductor devices decrease, there is a need for new technologies to improve integration density and maintain production yield while enhancing resistance and current driving characteristics, particularly in semiconductor devices with vertical channel transistors.
Innovation Solution
A semiconductor memory device is designed with vertical channel transistors, incorporating bit lines, channel patterns with horizontal and vertical portions, word lines with horizontal and vertical extensions, and gate insulating patterns to enhance integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are decreased to increase integration density, then integration density improves, but manufacturing precision and production yield deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the third dimension (vertical direction) to increase integration density. The vertical channel extends in the thickness direction of the substrate, allowing higher device density without compromising lateral manufacturing precision, thus resolving the contradiction between increased integration density and maintained production yield.
2Ease of manufacture
If conventional planar transistors are used, then manufacturing is easier, but resistance and current driving characteristics are insufficient
Solution Approach 1:
The invention adopts vertical channel transistors where the channel extends vertically through the substrate thickness, increasing the effective channel length without increasing lateral footprint. This dimensional change improves resistance and current driving characteristics while maintaining compatibility with existing manufacturing processes, thus resolving the contradiction between ease of manufacture and electrical performance.
Data Source
AI summary
A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.