3D Cross-Point Memory with Single-Crystalline BJT Selectors

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Solution Overview

Problem

Current 3D memory devices face challenges in achieving high current density and multi-state memory levels due to the limitations of semiconductor materials, particularly in cross-point memory arrays, where single-crystalline materials are not compatible with 3D stacking, and existing selector devices like p-n junction diodes are inadequate for high current control.

Innovation Solution

The method involves forming a stacked configuration of doped single-crystalline semiconductor layers to create bipolar junction transistor (BJT) devices, which include emitter, base, and collector layers, enabling higher current density and better control through the formation of pillars with extrinsic base layers, facilitating a cross-point memory cell array structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If single-crystalline materials are used for selector devices, then current density and control quality are improved, but compatibility with 3D stacking is lost

Engineering Contradiction:
Improvecurrent density and control qualityVSAvoidcompatibility with 3D stacking
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent transitions from planar 2D cross-point arrays to vertically stacked 3D structures by forming bipolar transistors with emitter, base, and collector layers stacked in the vertical dimension. This allows single-crystalline materials to be used while maintaining 3D stacking compatibility, as the crystalline structure is preserved through the vertical stacking process rather than requiring lateral expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite material structures by combining multiple doped semiconductor layers (emitter, base, collector) with different doping types and concentrations to form the bipolar transistor. This composite approach enables the use of single-crystalline materials throughout the stack while achieving the desired electrical characteristics through the composite layer structure.

Inventive Principle:
Principle #40Composite materials

2Device complexity

If p-n junction diodes are used as selector devices, then device simplicity is maintained, but current control capability is insufficient

Engineering Contradiction:
Improvedevice simplicityVSAvoidcurrent control capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the selector device into three distinct functional layers: emitter, base, and collector. This segmentation transforms the simple p-n junction diode into a bipolar transistor structure, where each layer performs a specific function. The base layer acts as the control terminal, enabling independent control of current flow between emitter and collector, thus significantly improving current control capability while maintaining reasonable device complexity.

Inventive Principle:
Principle #1Segmentation

3Productivity

If current density is increased for programming memory elements, then programming capability is improved, but demanding requirements are imposed on semiconductor material quality

Engineering Contradiction:
Improveprogramming capabilityVSAvoidsemiconductor material quality requirements
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the electrical parameters of the selector device by implementing a bipolar transistor structure with controlled doping concentrations in each layer. This allows the device to support high current densities required for programming while maintaining material quality within achievable manufacturing ranges. The doping parameters are optimized to enable high current density operation without requiring excessively high material perfection.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10903275B2Three-dimensional stackable multi-layer cross-point memory with single-crystalline bipolar junction transistor selectors
Publication Date: 2021.01.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10903275B2 patent drawing
  • US10903275B2 patent drawing
  • US10903275B2 patent drawing

AI summary

A method for manufacturing a semiconductor memory device includes forming a plurality of doped semiconductor layers in a stacked configuration on a dielectric layer. The plurality of doped semiconductor layers each comprise a single crystalline semiconductor material. In the method, a memory stack layer is formed on an uppermost doped semiconductor layer of the plurality of doped semiconductor layers, and the memory stack layer and a plurality of doped semiconductor layers are patterned into a plurality of pillars spaced apart from each other. The patterned plurality of doped semiconductor layers in each pillar of the plurality of pillars are components of a bipolar junction transistor device, and the plurality of pillars are parts of a memory cell array having a cross-point structure.